AD9874 Analog Devices, AD9874 Datasheet - Page 19

• Manufacturer Part Number: AD9874
• Description: Low Power IF Digitizing Subsystem
• Manufacturer: Analog Devices

Specifications of AD9874

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 26MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

As shown in Figure 4b, AD9874’s synchronous serial interface
(SSI) links the receive data stream to the DSP’s Serial Port
(SPORT). For AD9874 setup and register programming, the
device connects directly to ADSP-2153x’s SPI port. Dedicated
select lines (SEL) allow the ADSP-2153x to program and read
back registers of multiple devices using only one SPI port. The
DSP driver code pertaining to this interface is available on the
AD9874 web page
static/techSupport/designTools/evaluationBoards/
ad9874blackfinInterfacing.html).
POWER CONTROL
To allow power consumption to be minimized, the AD9874
possesses numerous SPI programmable power-down and bias
control bits. The AD9874 powers up with all of its functional
blocks placed into a standby state (i.e., STBY register default is
0xFF). Each major block may then be powered up by writing
a 0 to the appropriate bit of the STBY register. This scheme
provides the greatest flexibility for configuring the IC to a spe-
cific application as well as for tailoring the IC’s power-down and
wake-up characteristics. Table VI summarizes the function of
each of the STBY bits. Note that when all the blocks are in
standby, the master reference circuit is also put into standby,
and thus the current is reduced by a further 0.4 mA.
STBY
Bit
7:REF
6:LO
5:CKO
4:CK
3:GC
2:LNAMX LNA and Mixer OFF. CXVM, 8.2
1:Unused
0:ADC
NOTES
1
2
REV. A
Figure 4b. Example of AD9874 and ADSP-2153x Interface
Wake-up time is dependent on programming and/or external components.
When all blocks are in standby, the master reference circuit is also put into
standby, and thus the current is further reduced by 0.4 mA.
Effect
Voltage reference OFF;
all biasing shut down.
LO synthesizer OFF,
IOUTL three-state.
Clock Oscillator OFF.
Clock synthesizer OFF,
IOUTC three-state. Clock
buffer OFF if ADC is OFF.
Gain control DAC OFF.
GCP and GCN three-state.
CXVL, and CXIF three-state.
ADC OFF; Clock Buffer OFF 9.2
if CLK synthesizer OFF; VCM
three-state; Clock to the digital
filter halted; Digital outputs
static.
SPI
SSI
Table VI. Standby Control Bits
AD9874
(http://www.analog.com/Analog_Root/
CLKOUT
DOUTB
DOUTA
PC
PD
PE
FS
SCK
SEL
MOSI
MISO
RSCLK
RFS
DR
ADSP-2153x
Current
Reduction Wake-Up
(mA)
0.6
1.2
1.1
1.3
0.2
SPI-PORT
SERIAL
PORT
1
Time (ms)
<0.1 (C
= 4.7 nF)
Note 2
Note 2
Note 2
Depends
on C
<2.2
<0.1
GC
REF
–19–
The AD9874 also allows control over the bias current in the LNA,
mixer, and clock oscillator. The effects on current consumption
and system performance are described in the section dealing
with the affected block.
LO SYNTHESIZER
The LO Synthesizer shown in Figure 5 is a fully programmable
PLL capable of 6.25 kHz resolution at input frequencies up to
300 MHz and reference clocks of up to 25 MHz. It consists of a
low noise digital phase-frequency detector (PFD), a variable
output current charge pump (CP), a 14-bit reference divider,
programmable A and B counters, and a dual-modulus 8/9 pres-
caler. The A (3-bit) and B (13-bit) counters, in conjunction
with the dual 8/9 modulus prescaler, implement an N divider
with N = 8
(R Counter) allows selectable input reference frequencies, f
at the PFD input. A complete PLL (phase-locked loop) can be
implemented if the synthesizer is used with an external loop
filter and VCO (voltage controlled oscillator).
The A, B, and R counters can be programmed via the following
registers: LOA, LOB, and LOR. The charge pump output cur-
rent is programmable via the LOI register from 0.625 mA to
5.0 mA using the equation
An on-chip fast acquire function (enabled by the LOF bit)
automatically increases the output current for faster settling
during channel changes. The synthesizer may also be disabled
using the LO standby bit located in the STBY register.
f
The LO (and CLK) synthesizer works in the following manner.
The externally supplied reference frequency, f
and divided by the value held in the R counter. The internal
f
quency, f
DOWN pulses whose widths vary, depending upon the differ-
ence in phase and frequency of the detector’s input signals. The
UP/DOWN pulses control the charge pump, making current
available to charge the external low-pass loop filter when there is
a discrepancy between the inputs of the PFD. The output of the
low-pass filter feeds an external VCO whose output frequency,
f
that of f
The synthesized frequency is related to the reference frequency
and the LO register contents as follows:
Note that the minimum allowable value in the LOB register is 3
and its value must always be greater than that loaded into LOA.
REF
REF
LO
, is driven such that its divided down version, f
is then compared to a divided version of the VCO fre-
IPUMP
f
LO
BUFFER
REF
REF
LO
=
, thus closing the feedback loop.
(
. The phase/frequency detector provides UP and
8
=
×
B + A. In addition, the 14-bit reference counter
(
LOB
LOI
Figure 5. LO Synthesizer
LOR
LOA, LOB
R
COUNTERS
+
+
1
f
LOA
REF
A, B
)
×
0 625
FREQUENCY
) /
.
DETECTOR
f
PHASE/
LO
LOR
mA
×
8/9
f
REF
REF
ACQUIRE
AD9874
BUFFER
CHARGE
FAST
, is buffered
PUMP
LO
LO
, matches
TO EXTERNAL
FILTER
LOOP
f
FROM
VCO
LO
REF
(2)
(3)
,