AD7898 Analog Devices, AD7898 Datasheet - Page 12

• Manufacturer Part Number: AD7898
• Description: 5V, 12-Bit, Serial 220 kSPS ADC in a 8-Lead Package
• Manufacturer: Analog Devices

Specifications of AD7898

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 220kSPS
• Interface: Ser
• Analog Input Type: SE-Bip
• Ain Range: Bip (Vref),Bip (Vref) x 4,Bip 10V,Bip 2.5V
• Adc Architecture: SAR
• Pkg Type: SOIC

AD7898
Mode 1 Operation
The timing diagram in Figure 8 shows the AD7898 operating in
Mode 1. The serial clock provides the conversion clock and also
controls the transfer of information from the AD7898 during
conversion.
CS initiates the data transfer and conversion process. The fall-
ing edge of CS puts the track-and-hold into hold mode, takes
the bus out of three-state and the analog input is sampled at
this point. The conversion is also initiated at this point and will
require 16 SCLK cycles to complete. On the 14th SCLK falling
edge the track-and-hold will go back into track. On the 16th
SCLK falling edge the SDATA line will go back into three-
state. If the rising edge of CS occurs before 16 SCLKs have
elapsed then the conversion will be terminated and the SDATA
line will go back into three-state, otherwise SDATA returns to
three-state on the 16th SCLK falling edge as shown in Figure 8.
Sixteen serial clock cycles are required to perform the conver-
sion process and to access data from the AD7898. CS going
low provides the first leading zero to be read in by the micro-
controller or DSP. The remaining data is then clocked out by
subsequent SCLK falling edges beginning with the second lead-
ing zero, thus the first falling clock edge on the serial clock has
the first leading zero provided and also clocks out the second
leading zero. The final bit in the data transfer is valid on the
16th falling edge, having being clocked out on the previous (15th)
falling edge. It is also possible to read in data on each SCLK
rising edge, although the first leading zero will still have to be
read on the first SCLK falling edge after the CS falling edge.
Therefore the first rising edge of SCLK after the CS falling edge
would provide the second leading zero and the 15th rising SCLK
edge would have DB0 provided if the application requires data
to be read on each rising edge.
Mode Selection
Upon power-up, the default mode of operation of the AD7898
is Mode 0. The part will continue to operate in Mode 0 as out-
lined in the Mode 0 Operation section, provided an SCLK edge
is not applied to the AD7898 during the conversion time and
when CONVST is low. If an SCLK edge is applied to the
AD7898 during t
Mode 0, the part will switch to operate in Mode 1 as shown in
Figure 9. The serial interface will now operate as described in
the Mode 1 operation section. The AD7898 will return to
Mode 0 operation from Mode 1 if CS is brought low and then
subsequently high without any SCLK edges provided while CS
SDATA
SCLK
CS
THREE-STATE
CONVERT
t
2
Z
1
t
and when CONVST is low while in
3
ZERO
FOUR LEADING ZEROS
2
ZERO
Figure 8. Serial Interface Timing Diagram Mode 1
3
ZERO
4
DB11
t
4
t
6
t
CONVERT
5
DB10
6
t
5
–12–
DB9
is low (see Figure 10). If any SCLK edges are applied to the
device while CS is low when in Mode 1, the part will remain in
Mode 1 and may or may not enter a power-down mode as
determined by the number of SCLKs applied, see Power-Down
Mode section.
If the part is operating in Mode 0 and a glitch occurs on the
SCLK line while CONVST is low, the part will enter Mode 1
and the conversion that was initiated by CONVST going low
will be terminated. The part will now be operating in Mode 1,
but Mode 0 signals will still be applied from the processor.
When CS goes low and no SCLK is applied, the part will revert
back to Mode 0 operation. This avoids accidental changing of
modes due to glitches on the SCLK line.
Power-Down Mode
The power-down mode is only accessible when in Mode 1
operation. This mode is intended for use in applications where
slower throughput rates are required; either the ADC is pow-
ered down between each conversion, or a series of conversions
may be performed at a high throughput rate and the ADC is
powered down for a relatively long duration between these
bursts of several conversions. When the AD7898 is in power-
down, all analog circuitry is powered down.
t
7
CONVST
SCLK
14
Figure 10. Entering Mode 0 from Mode 1
Figure 9. Entering Mode 1 from Mode 0
CONVERSION IS
INITIATED IN
MODE 0
SCLK
15
CS
t
DB0
8
t
1
16
t
CONVERT
AD7898 ENTERS
t
THREE-STATE
1
AD7898 ENTERS
MODE 0
CONVERSION
TERMINATES,
= 3.3 s
MODE 1
t
QUIET
REV. A