AD9226 Analog Devices, AD9226 Datasheet - Page 14

• Manufacturer Part Number: AD9226
• Description: 12-Bit, 65 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9226

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 65MSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p,1 V p-p,2 V p-p,Uni (Vref),Uni 1.0V,Uni 2.0V
• Adc Architecture: Pipelined
• Pkg Type: QFP,SOP

THEORY OF OPERATION
The AD9226 is a high-performance, single-supply 12-bit ADC.
The analog input of the AD9226 is very flexible allowing for both
single-ended or differential inputs of varying amplitudes that can
be ac- or dc-coupled.
It utilizes a nine-stage pipeline architecture with a wideband,
sample-and-hold amplifier (SHA) implemented on a cost-
effective CMOS process. A patented structure is used in the
SHA to greatly improve high frequency SFDR/distortion. This
also improves performance in IF undersampling applications.
Each stage of the pipeline, excluding the last stage, consists of a
low resolution flash ADC connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier amplifies the difference between the reconstructed DAC
output and the flash input for the next stage in the pipeline. One
bit of redundancy is used in each of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a
flash ADC.
Factory calibration ensures high linearity and low distortion.
ANALOG INPUT OPERATION
Figure 3 shows the equivalent analog input of the AD9226 which
consists of a 750 MHz differential SHA. The differential input
structure of the SHA is highly flexible, allowing the device to be
easily configured for either a differential or single-ended input.
The analog inputs, VINA and VINB, are interchangeable with
the exception that reversing the inputs to the VINA and VINB
pins results in a data inversion (complementing the output word).
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest input
signal voltage span (i.e., 2 V input span) and matched input
impedance for VINA and VINB. Only a slight degradation in
dc linearity performance exists between the 2 V and 1 V input
spans.
High frequency inputs may find the 1 V span better suited to
achieve superior SFDR performance. (See Typical Perfor-
mance Characteristics.)
The ADC samples the analog input on the rising edge of the clock
input. During the clock low time (between the falling edge and
rising edge of the clock), the input SHA is in the sample mode;
during the clock high time it is in hold. System disturbances just
prior to the rising edge of the clock and/or excessive clock jitter
on the rising edge may cause the input SHA to acquire the wrong
value and should be minimized.
When the ADC is driven by an op amp and a capacitive load is
switched onto the output of the op amp, the output will momen-
tarily drop due to its effective output impedance. As the output
recovers, ringing may occur. To remedy the situation, a series
resistor can be inserted between the op amp and the SHA
input as shown in Figure 4. A shunt capacitance also acts like
a charge reservoir, sinking or sourcing the additional charge
required by the hold capacitor, C
transients seen at the op amp’s output.
The optimum size of this resistor is dependent on several factors,
including the ADC sampling rate, the selected op amp, and the
particular application. In most applications, a 30 Ω to 100 Ω
resistor is sufficient.
For noise-sensitive applications, the very high bandwidth of the
AD9226 may be detrimental and the addition of a series resistor
AD9226
H
, further reducing current
and/or shunt capacitor can help limit the wideband noise at the
ADC’s input by forming a low-pass filter. The source imped-
ance driving VINA and VINB should be matched. Failure to
provide matching will result in degradation of the AD9226’s
SNR, THD, and SFDR.
OVERVIEW OF INPUT AND REFERENCE
CONNECTIONS
The overall input span of the AD9226 is equal to the potential
at the VREF pin. The VREF potential may be obtained from
the internal AD9226 reference or an external source (see
Reference Operation section).
In differential applications, the center point of the span is
obtained by the common-mode level of the signals. In single-
ended applications, the center point is the dc potential applied
to one input pin while the signal is applied to the opposite input
pin. Figures 5a–5f show various system configurations.
DRIVING THE ANALOG INPUTS
The AD9226 has a very flexible input structure allowing it to
interface with single-ended or differential input interface circuitry.
The optimum mode of operation, analog input range, and asso-
ciated interface circuitry will be determined by the particular
applications performance requirements as well as power sup-
ply options.
DIFFERENTIAL DRIVER CIRCUITS
Differential operation requires that VINA and VINB be simulta-
neously driven with two equal signals that are 180 out of phase
with each other.
Differential modes of operation (ac- or dc-coupled input) provide
the best THD and SFDR performance over a wide frequency
range. They should be considered for the most demanding
spectral-based applications (e.g., direct IF conversion to digital).
VINB
VINA
V
V
CC
EE
10 F
C
C
C
C
PIN
PAR
PIN
PAR
33
R
0.1 F
S
Q
Q
S1
S1
33
R
S
15pF
Q
H1
C
C
VINA
VINB
VREF
SENSE
REFCOM
S
S
AD9226
Q
Q
C
C
H
S2
S2
H