AD7707 Analog Devices, AD7707 Datasheet - Page 22

• Manufacturer Part Number: AD7707
• Manufacturer: Analog Devices

Specifications of AD7707

• Resolution (bits): 16bit
• # Chan: 3
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Bip
• Ain Range: Bip (Vref)/(PGA Gain),Bip 10V,Bip 5.0V,Uni (Vref)/(PGA Gain),Uni 10V,Uni 5.0V
• Adc Architecture: Sigma-Delta
• Pkg Type: SOIC,SOP

AD7707
Table 24. Output Update Rates
CLK
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
Data Register (RS2, RS1, RS0 = 0, 1, 1)
The data register on the part is a 16-bit read-only register that
contains the most up-to-date conversion result from the AD7707.
If the communications register sets up the part for a write
operation to this register, a write operation must actually take
place to return the part to where it is expecting a write operation to
the communications register. However, the 16 bits of data
written to the part are ignored by the AD7707.
Test Register (RS2, RS1, RS0 = 1, 0, 0); Power-On/Reset
Status: 0x00
The part contains a est egister that is used when testing the
device. The user is advised not to change the status of any of the
bits in this register from the default (power-on or RESET ) status
of all 0s because the part will be placed in one of its test modes
and will not operate correctly.
Zero-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 0);
Power-On/Reset Status: 0x1F4000
The AD7707 contains independent sets of zero-scale registers,
one for each of the input channels. Each of these registers is a
24-bit read/write register; 24 bits of data must be written; otherwise,
no data is transferred to the register. This register is used in
conjunction with its associated full-scale register to form a
register pair. These register pairs are associated with input
channel pairs as outlined in Table 17. Although the part is set
up to allow access to these registers over the digital interface,
the part itself no longer has access to the register coefficients to
Assumes correct clock frequency on the MCLK IN pin with the CLKDIV bit set appropriately.
1
FS2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output Update Rate
20 Hz
25 Hz
100 Hz
200 Hz
50 Hz
60 Hz
250 Hz
500 Hz
4.054 Hz
4.23 Hz
4.84 Hz
4.96 Hz
10 Hz
10.34 Hz
11.90 Hz
12.2 Hz
Rev. B | Page 22 of 52
correctly scale the output data. As a result, there is a possibility
that after accessing the calibration registers (either read or write
operation) the first output data read from the part may contain
incorrect data. In addition, a write to the calibration register
should not be attempted while a calibration is in progress. These
eventualities can be avoided by taking the FSYNC bit in the
setup register high before the calibration register operation and
taking it low after the operation is complete.
Full-Scale Calibration Register (RS2, RS1, RS0 = 1, 1, 1);
Power-On/Reset Status: 0x5761AB
The AD7707 contains independent sets of full-scale registers,
one for each of the input channels. Each of these registers is a
24-bit read/write register; 24 bits of data must be written; otherwise,
no data is transferred to the register. This register is used in
conjunction with its associated zero-scale register to form a
register pair. These register pairs are associated with input channel
pairs as outlined in Table 17. Although the part is set up to
allow access to these registers over the digital interface, the part
itself no longer has access to the register coefficients to correctly
scale the output data. As a result, there is a possibility that after
accessing the calibration registers (either read or write
operation) the first output data read from the part may contain
incorrect data. In addition, a write to the calibration register
should not be attempted while a calibration is in progress. These
eventualities can be avoided by taking
register high before the calibration register operation and taking
it low after the operation is complete.
−3 dB Filter Cutoff
1.06 Hz
1.11 Hz
1.27 Hz
1.3 Hz
2.71 Hz
3.13 Hz
3.2 Hz
5.24 Hz
6.55 Hz
26.2 Hz
52.4 Hz
13.1 Hz
15.7 Hz
65.5 Hz
131 Hz
2.62 Hz
FSYNC bit in the setup