AD7706 Analog Devices, AD7706 Datasheet - Page 8

• Manufacturer Part Number: AD7706
• Description: 3V/5V, 1mW, 3-Channel Pseudo Differential, 16-Bit Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7706

• Resolution (bits): 16bit
• # Chan: 3
• Sample Rate: n/a
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip (Vref)/(PGA Gain),Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC,SOP

AD7705/AD7706
TIMING CHARACTERISTICS
V
Table 2. Timing Characteristics
Parameter
f
t
t
t
t
Read Operation
Write Operation
1
2
3
4
5
6
7
CLKIN
CLKIN LO
CLKIN HI
1
2
Sample tested at 25°C to ensure compliance. All input signals are specified with t
See Figure 19 and Figure 20.
The f
higher current than specified, and possibly become uncalibrated.
The AD7705/AD7706 are production tested with f
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
DRDY returns high upon completion of the first read from the device after an output update. The same data can be reread while DRDY is high, but care should be
taken that subsequent reads do not occur close to the next output update.
DD
t
t
t
t
t
t
t
t
t
t
t
t
t
t
3
4
5
6
7
8
9
10
11
12
13
14
15
16
5
6
= 2.7 V to 5.25 V; GND = 0 V; f
3, 4
CLKIN
duty cycle range is 45% to 55%. f
Limit at T
(B Version)
400
2.5
0.4 × t
0.4 × t
500 × t
100
0
120
0
80
100
100
100
0
10
60
100
100
120
30
20
100
100
0
CLKIN
CLKIN
CLKIN
MIN
1, 2
, T
CLKIN
CLKIN
MAX
must be supplied whenever the AD7705/AD7706 are not in standby mode. If no clock is present, the devices can draw
= 2.4576 MHz; Input Logic 0 = 0 V, Logic 1 = V
CLKIN
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
TO OUTPUT
at 2.4576 MHz (1 MHz for some I
Unit
kHz min
MHz max
ns min
ns min
ns nom
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
PIN
50pF
Conditions/Comments
Master clock frequency (crystal oscillator or externally supplied)
For specified performance
Master clock input low time, t
Master clock input high time
DRDY high time
RESET pulse width
DRDY to CS setup time
CS falling edge to SCLK rising edge setup time
SCLK falling edge to data valid delay
V
V
SCLK high pulse width
SCLK low pulse width
CS rising edge to SCLK rising edge hold time
Bus relinquish time after SCLK rising edge
V
V
SCLK falling edge to DRDY high
CS falling edge to SCLK rising edge setup time
SCLK high pulse width
SCLK low pulse width
CS rising edge to SCLK rising edge hold time
Rev. C | Page 8 of 44
Data valid to SCLK rising edge setup time
Data valid to SCLK rising edge hold time
DD
DD
DD
DD
= 5 V
= 3.0 V
= 5 V
= 3.0 V
R
= t
I
I
SINK
SOURCE
F
= 5 ns (10% to 90% of V
DD
(800μA AT V
100μA AT V
tests). They are guaranteed by characterization to operate at 400 kHz.
100mA AT V
(200μA AT V
1.6V
DD
DD
= 3V)
DD
= 5V
DD
= 3V)
= 5V
DD
CLKIN
, unless otherwise noted.
DD
7
) and timed from a voltage level of 1.6 V.
= 1/f
CLKIN
OL
or V
OH
limits.