AD7731 Analog Devices, AD7731 Datasheet

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... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. GENERAL DESCRIPTION The AD7731 is a complete analog front-end for process control applications. The device has a proprietary programmable gain front end that allows it to accept a range of input signal ranges, including low level signals, directly from a transducer ...

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... AD7731–SPECIFICATIONS Parameter STATIC PERFORMANCE (CHP = Missing Codes 2 Output Noise and Update Rates Integral Nonlinearity 2 Offset Error 2 Offset Drift vs. Temperature 5 Offset Drift vs. Time 2, 6 Positive Full-Scale Error Positive Full-Scale Drift vs. Temp 5 Positive Full-Scale Drift vs. Time 2, 9 Gain Error Gain Drift vs ...

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... A max 67.5 mW max 125 W max –3– AD7731 Conditions/Comments HIREF Bit of Mode Register = 0 HIREF Bit of Mode Register = 1 HIREF Bit of Mode Register = 0 HIREF Bit of Mode Register = 1 NO REF Bit Active If VREF Below This Voltage NO REF Bit Inactive If VREF Above This Voltage ...

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... AD7731 NOTES 1 Temperature Range: – + Sample tested during initial release missing codes performance with CHP = 0 and SKIP = bits. 4 The offset (or zero) numbers with CHP = 0 can precalibration. Internal zero-scale calibration reduces this typical. Offset numbers with CHP = 1 are typically 3 V precalibration ...

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... AD7731BR-REEL7 AD7731BRZ AD7731BRZ-REEL AD7731BRZ-REEL7 AD7731BRU AD7731BRU-REEL AD7731BRU-REEL7 AD7731BRUZ AD7731BRUZ-REEL AD7731BRUZ-REEL7 EVAL-AD7731EBZ Figure 1. Load Circuit for Access Time and Bus Relinquish Time ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...

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... AGND DGND POL RDY OUTPUT DRIVERS CALIBRATION MICROCONTROLLER THE AIN3 AND AIN4 INPUT CHANNELS CAN BE THE AD7731 OFFERS A RECONFIGURED TO BECOME NUMBER OF DIFFERENT TWO OUTPUT DIGITAL PORT CALIBRATION OPTIONS LINES THAT CAN BE INCLUDING SELF AND PROGRAMMED OVER THE SYSTEM CALIBRATION SERIAL INTERFACE ...

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... Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer serial data to or from the AD7731. This serial clock can be a continuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans- mitted to or from the AD7731 in smaller batches of data ...

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... If the active edge for the processor is a low-to-high SCLK transition, this input should be high. In this mode, the AD7731 puts out data on the DATA OUT line in a read operation on a high-to-low transition of SCLK and clocks in data from the DATA IN line in a write operation on a low-to- high transition of SCLK ...

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... Logic output. Used as a status output in both conversion mode and calibration mode. In conversion mode, a logic low on this output indicates that a new output word is available from the AD7731 data register. The RDY pin will return high upon completion of a read operation of a full output word data read has taken place after an output update, the RDY line will return high prior to the next output update, remain high while the update is taking place and return low again ...

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... Output Noise (CHP = 0, SKIP = 1) Table I shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in nonchop mode (CHP of Filter Register = 0) and with the second filter bypassed (SKIP of Filter Register = 1). The table is generated with a master clock frequency of 4 ...

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... Output Noise (CHP = 1, SKIP = 0) Table III shows the output rms noise for some typical output update rates and –3 dB frequencies for the AD7731 when used in chopping mode (CHP of Filter Register = 1) and with the second filter included in the loop. The numbers are generated with a mas- ter clock frequency of 4 ...

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... AD7731 Register Name Type Size Communications Write Only 8 Bits Register Status Register Read Only 8 Bits Data Register Read Only 16 Bits or 24 Bits 000000 Hex Mode Register ...

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... Communications Register. In situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with DIN high, returns the AD7731 to this default state by resetting the part. Table VI outlines the bit designations for the Communications Register. CR0 through CR7 indicate the bit location, CR denoting the bits are in the Communications Register ...

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... Status Register. SR0 through SR7 indicate the bit location, SR denoting the bits are in the Status Register. SR7 de- notes the first bit of the data stream. Figure 5 shows a flowchart for reading from the registers on the AD7731. The number in brackets indicates the power-on/reset default status of that bit. ...

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... Mode Register. MR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers on the part. ...

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... Sync (Idle) Mode. In this mode, the modulator and filter are held in reset mode and the AD7731 is not processing any new samples or data. Placing the part in this mode is equivalent to exerting the SYNC input pin. However, exerting the SYNC does not actually force these mode bits The part re- turns to this mode after a calibration or after a conversion in Single Conversion Mode ...

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... V to +1.28 V –17– AD7731 Input Range B/U Bit = + + + + +160 +320 +640 +1.28 V Power-On/Reset Default ...

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... Filter Register. FR0 through FR15 indicate the bit location, FR denoting the bits are in the Filter Register. FR15 denotes the first bit of the data stream. The number in brackets indicates the power-on/reset default status of that bit. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers on the part. ...

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... Mode Register). During subsequent conversions, the contents of this register are subtracted from the filter output prior to gain scaling being performed on the word. Figure 5 shows a flowchart for reading from the registers on the AD7731 and Figure 6 shows a flowchart for writing to the registers on the part. ...

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... AD7731 READING FROM AND WRITING TO THE ON-CHIP REGISTERS The AD7731 contains a total of twelve on-chip registers. These registers are all accessed over a three-wire interface result, addressing of registers is via a write operation to the topmost register on the part, the Communications Register. Figure 5 shows a flowchart for reading from the different registers on the part summarizing the sequence and the words to be written to access each of the registers ...

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... CALIBRATION OPERATION SUMMARY The AD7731 contains a number of calibration options as outlined previously. Table XVI summarizes the calibration types, the op- erations involved and the duration of the operations. There are two methods of determining the end of calibration. The first is to monitor the hardware RDY pin using either interrupt-driven or polling routines. The second method software poll of the RDY bit in the Status Register ...

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... AD7731 CIRCUIT DESCRIPTION The AD7731 is a sigma-delta A/D converter with on-chip digital filtering, intended for the measurement of wide dynamic range, low-frequency signals such as those in strain-gage, pressure transducer, temperature measurement, industrial control or pro- cess control applications. It contains a sigma-delta (or charge- balancing) ADC, a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter and a bidirectional serial communications port ...

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... AIN(–) input. For example, if AIN(–) is +2.5 V and the AD7731 is configured for an analog input range +20 mV, the input voltage range on the AIN(+) input is +2 +2. AIN(–) is +2.5 V and the AD7731 is configured for an analog input range of 1.28 V, the analog input range on the AIN(+) input is +1. +3.78 V (i.e., 2.5 V Bipolar or unipolar options are chosen by programming the B/U bit of the Mode Register ...

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... AD7731 include the AD780, REF43 and REF192. If any of these references are used as the reference source for the AD7731, the HIREF bit should be set generally rec- ommended to decouple the output of these references to further reduce the noise level. ...

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... Filter Register and f is the modulator frequency MOD and is 1/16th of the master clock frequency. Thus for a given SF word the output rate from the AD7731 is three times faster with CHP = 0 than CHP = 1. The various filter stages and options are discussed in the follow- ing sections. ...

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... For example, if the line frequency is 50 Hz, an output update rate should not be chosen as it will significantly reduce the AD7731’s line frequency rejection (the 50 Hz will appear component with only 6 dB attenuation). However, choos- ing the output rate (SF = 1707) will give better than 90 dB attenuation of the aliased line frequency ...

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... The response is shown from dc to 100 Hz. The re- jection and better than 88 dB. The –3 dB frequency for the frequency response of the AD7731 with the second stage filter set for normal FIR operation and chop mode enabled is determined by the following relationship ...

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... FASTStep™ mode and provides an output result in 2 Note, if the FAST bit is set and the part operated in single con- version mode, the AD7731 will continue to output results until the STDY bit goes to 0. Table XVIII. Time to First and Subsequent Outputs Follow- ...

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... Output Rate; with CHP = 0, the duration is 24 1/Output Rate. At this time the MD2, MD1 and MD0 bits in the Mode Register return (Sync or Idle Mode for the AD7731). The RDY line goes high when calibration is initiated and re- turns low when calibration is complete. Note, the part has not performed a conversion at this time ...

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... Output Rate; with CHP = 0, the duration this time the MD2, MD1 and MD0 bits in the Mode Regis- ter return (Sync or Idle Mode for the AD7731). The RDY line goes high when calibration is initiated and returns low when calibration is complete. Note, the part has not performed a conversion at this time ...

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... FS and a maximum value of 2.1 FS. However, the span (which is the difference between the bottom of the AD7731’s input range and the top of its input range) has to take into account the limitation on the positive full-scale voltage. The amount of offset which can be accommo- dated depends on whether the unipolar or bipolar mode is being used ...

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... SYNC inputs will synchronize their operation. This would nor- mally be done after each AD7731 has performed its own cali- bration or has had calibration coefficients loaded to it. The *The AD7731 has a capacitance MCLK IN and MCLK OUT. output updates will then be synchronized with the maximum possible difference between the output updates of the individual AD7731s being one MCLK IN cycle ...

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... The analog ground plane should be allowed to run under the AD7731 to avoid noise coupling. The power supply lines to the AD7731 should use as large a trace as pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals like ...

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... SCLK. For POL = 0, the first clock edge which clocks data from the microcontroller onto the DIN line of the AD7731 is a rising edge then clocked into the input shift register on the next falling edge of SCLK ...

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... Figure 16 shows a timing diagram for a read operation from the output shift register of the AD7731. With the POL input at a logic high, the data is clocked out of the output shift register on the falling edge of SCLK. With the POL input at a logic low, the data is clocked out of the output shift register on the rising edge of SCLK ...

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... AD7731 CONFIGURING THE AD7731 The AD7731 contains twelve on-chip registers which can be accessed via the serial interface. Figure 5 and Figure 6 have outlined a flowchart for the reading and writing of these registers. Table XIX and Table XX outline sample pseudo-code for some commonly used routines. The required operating conditions will dictate the values loaded to the Mode and Filter Registers. The values given here are for example purposes only ...

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... REV. A REV. 0 that the SCLK idle high, the CPOL bit of the 68HC11 should be set to a logic 1 and the POL input of the AD7731 should be hard-wired to a logic high. The AD7731 is not capable of full duplex operation. If the AD7731 is configured for a write operation, no data appears on the DATA OUT lines even when the SCLK input is active ...

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... The POL pin of the AD7731 is hard-wired low. Because the SCLK from the ADSP-2105 is a continuous clock, the CS of the AD7731 must be used to gate off the clock once the transfer is complete. The CS for the AD7731 is active when either the RFS or TFS outputs from the ADSP-2105 are active ...

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... APPLICATIONS The on-chip PGA allows the AD7731 to handle analog input voltage ranges from 1.28 V. This makes the AD7731 suitable for a range of application areas from handling signals directly from a transducer to processing fully-conditioned full- scale inputs. Some of these applications are discussed in the following sections ...

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... AD7731 is in temperature measurement. Figure 23 outlines a connection between a thermocouple and the AD7731. In order to place the differential voltage from the AD7731 on a suitable common-mode voltage, the AIN2 input of the AD7731 is biased up at the reference voltage, +2.5 V. EXCITATION VOLTAGE = +5V IN+ OUT+ OUT– ...

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... THERMOCOUPLE JUNCTION + REF IN (+) V AD780 OUT REF IN (–) GND Figure 23. Temperature Measurement Using the AD7731 400 A REF IN (+) R1 6.25k R REF IN (– RTD AGND L4 DGND REV. A REV 100nA AIN1 AIN2 BUFFER SIGMA- ...

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... The example shown is a system that is driven from 5 V sup- plies. In such a circuit, two issues must be addressed. The first is how to get the AD7731 to handle input voltages below ground and the second is how to generate a suitable reference voltage for the AD7731. The circuit of Figure 25 attempts to address these two issues simultaneously. The AD7731’ ...

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... CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Internal Zero-Scale Calibration . . . . . . . . . . . . . . . . . . . . 29 Internal Full-Scale Calibration . . . . . . . . . . . . . . . . . . . . 30 System Zero-Scale Calibration . . . . . . . . . . . . . . . . . . . . 30 System Full-Scale Calibration . . . . . . . . . . . . . . . . . . . . . 30 Span and Offset Limits . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power-Up and Calibration . . . . . . . . . . . . . . . . . . . . . . . 31 Drift Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 USING THE AD7731 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clocking and Oscillator Circuit . . . . . . . . . . . . . . . . . . . . 32 System Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . 32 Single-Shot Conversions . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Grounding and Layout ...

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... AD7731 0.210 (5.33) MAX 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 OUTLINE DIMENSIONS 24-Lead Plastic Dual In-Line Package [PDIP] Dimensions shown in inches and (millimeters) Narrow Body (N-24-1) 1.280 (32.51) 1.250 (31.75) 1.230 (31.24 0.280 (7.11) 0.250 (6.35) 1 0.240 (6.10) 12 0.100 (2.54) BSC 0.060 (1.52) MAX 0.015 (0.38) 0.015 (0.38) MIN ...