AD9280

Manufacturer Part NumberAD9280
Description8-Bit, Complete, 32 MSPS A/D Converter
ManufacturerAnalog Devices
AD9280 datasheet
 


Specifications of AD9280

Resolution (bits)8bit# Chan1
Sample Rate32MSPSInterfacePar
Analog Input TypeDiff-Uni,SE-UniAin Range1 V p-p,2 V p-p
Adc ArchitecturePipelinedPkg TypeSOP
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FEATURES
CMOS 8-Bit 32 MSPS Sampling A/D Converter
Pin-Compatible with AD876-8
Power Dissipation: 95 mW (3 V Supply)
Operation Between +2.7 V and +5.5 V Supply
Differential Nonlinearity: 0.2 LSB
Power-Down (Sleep) Mode
Three-State Outputs
Out-of-Range Indicator
Built-In Clamp Function (DC Restore)
Adjustable On-Chip Voltage Reference
IF Undersampling to 135 MHz
PRODUCT DESCRIPTION
The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS
analog-to-digital converter with an on-chip sample-and-hold
amplifier and voltage reference. The AD9280 uses a multistage
differential pipeline architecture at 32 MSPS data rates and
guarantees no missing codes over the full operating temperature
range.
The input of the AD9280 has been designed to ease the devel-
opment of both imaging and communications systems. The user
can select a variety of input ranges and offsets and can drive the
input either single-ended or differentially.
The sample-and-hold amplifier (SHA) is equally suited for both
multiplexed systems that switch full-scale voltage levels in suc-
cessive channels and sampling single-channel inputs at frequen-
cies up to and beyond the Nyquist rate. AC-coupled input
signals can be shifted to a predetermined level, with an onboard
clamp circuit. The dynamic performance is excellent.
The AD9280 has an onboard programmable reference. An
external reference can also be chosen to suit the dc accuracy and
temperature drift requirements of the application.
CLAMP
CLAMP
VINA
REFTF
REFTS
REFBS
REFBF
VREF
REFSENSE
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Complete 8-Bit, 32 MSPS, 95 mW
A single clock input is used to control all internal conversion
cycles. The digital output data is presented in straight binary
output format. An out-of-range signal (OTR) indicates an over-
flow condition which can be used with the most significant bit
to determine low or high overflow.
The AD9280 can operate with a supply range from +2.7 V to
+5.5 V, ideally suiting it for low power operation in high speed
applications.
The AD9280 is specified over the industrial (–40 C to +85 C)
temperature range.
PRODUCT HIGHLIGHTS
Low Power
The AD9280 consumes 95 mW on a 3 V supply (excluding the
reference power). In sleep mode, power is reduced to below
5 mW.
Very Small Package
The AD9280 is available in a 28-lead SSOP package.
Pin Compatible with AD876-8
The AD9280 is pin compatible with the AD876-8, allowing
older designs to migrate to lower supply voltages.
300 MHz Onboard Sample-and-Hold
The versatile SHA input can be configured for either single-
ended or differential inputs.
Out-of-Range Indicator
The OTR output bit indicates when the input signal is beyond
the AD9280’s input range.
Built-In Clamp Function
Allows dc restoration of video signals.
FUNCTIONAL BLOCK DIAGRAM
CLK
DRVDD
IN
AVDD
SHA
SHA
GAIN
SHA
GAIN
SHA
A/D
D/A
A/D
D/A
A/D
CORRECTION LOGIC
OUTPUT BUFFERS
AD9280
1V
AVSS
DRVSS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
CMOS A/D Converter
AD9280
STBY
GAIN
SHA
GAIN
MODE
A/D
THREE-
D/A
A/D
D/A
STATE
OTR
D7 (MSB)
D0 (LSB)
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc.,
2010

AD9280 Summary of contents

  • Page 1

    ... The AD9280 is specified over the industrial (– +85 C) temperature range. PRODUCT HIGHLIGHTS Low Power The AD9280 consumes supply (excluding the reference power). In sleep mode, power is reduced to below 5 mW. Very Small Package The AD9280 is available in a 28-lead SSOP package. ...

  • Page 2

    ... AD9280–SPECIFICATIONS Parameter RESOLUTION CONVERSION RATE DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error REFERENCE VOLTAGES Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage 1 Reference Input Resistance ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (– ...

  • Page 3

    ... CPW REFTS 10k AD9280 REFTF 10k REFBF 0 REFBS MODE a. Figure 1. Equivalent Input Load –3– AD9280 Units Condition Output = GND to VDD Cycles mV CLAMPIN = +0 +2 (Period = 63 AD9280 4.2k b. ...

  • Page 4

    ... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9280 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

  • Page 5

    ... Reference Select CLAMP HI: Enable Clamp Mode. LO: No Clamp CLAMPIN Clamp Reference Input REFTS Top Reference REFTF Top Reference Decoupling MODE Mode Select REFBF Bottom Reference Decoupling REFBS Bottom Reference VREF Internal Reference Output AIN Analog Input AVDD Analog Supply –5– AD9280 ...

  • Page 6

    ... AD9280 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB before the first code transi- tion. “Full scale” is defined as a level 1 1/2 LSB beyond the last code transition ...

  • Page 7

    ... CLOCK = 32MHz 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 70 90 0E+0 Figure 12. Single-Tone Frequency Domain –7– AD9280 CLOCK FREQUENCY – MHz N–1 N N+1 CODE Figure 11. Grounded Input Histogram F = 1MHz IN F ...

  • Page 8

    ... OPERATIONAL MODES The AD9280 is designed to allow optimal performance in a wide variety of imaging, communications and instrumentation applications, including pin compatibility with the AD876-8 A/D. To realize this flexibility, internal switches on the AD9280 are used to reconfigure the circuit into different modes ...

  • Page 9

    ... VREF is determined by the internal reference or brought in externally by the user. The best noise performance may be obtained by operating the AD9280 with input range. The best distortion perfor- mance may be obtained by operating the AD9280 with input range. REFERENCE OPERATION The AD9280 can be configured in a variety of reference topolo- gies. The simplest configuration is to use the AD9280’ ...

  • Page 10

    ... VOLTAGE IS DERIVED FROM INTERNAL OR EXTERNAL REF AD9280 AIN SHA AVDD/2 10k 10k REFTS A2 4.2k REFBS A/D TOTAL 10k CORE INTERNAL 10k REF c. Differential Mode 1.0 F 0.1 F AD9280 ) B 0.1 F 1.0 F Figure 16. –10– AD9280 MODE AIN SHA 10k REFTF 10k A2 0.1 F A/D 4.2k CORE TOTAL 10k INTERNAL 10k ...

  • Page 11

    ... REFTS = reference top, sense REFBS = reference bottom, sense INTERNAL REFERENCE OPERATION Figures 18, 19 and 20 show sample connections of the AD9280 internal reference in its most common configurations. (Figures 18 and 19 illustrate top/bottom mode while Figure 20 illustrates center span mode). Figure 29 shows how to connect the AD9280 for 1 V p-p differential operation ...

  • Page 12

    ... EXTERNAL REFERENCE OPERATION Using an external reference may provide more flexibility and improve drift and accuracy. Figures 21 through 23 show ex- amples of how to use an external reference with the AD9280. To use an external reference, the user must disable the internal reference amplifier by connecting the REFSENSE pin to VDD. ...

  • Page 13

    ... The video signal must be dc restored from 3-volt range down 2-volt range. Configuring the AD9280 for a one volt input span with an input range from volts (see Figure 24), the CLAMPIN voltage can be set to 1 volt with an external voltage or by direct connection to REFBS ...

  • Page 14

    ... AD9280’s internal clamp. See Clamp Operation. There are additional considerations when choosing the resistor values. The ac-coupling capacitors integrate the switching tran- sients present at the input of the AD9280 and cause a net dc bias current less. For applica- bias current increases as the signal magnitude deviates from V midscale and the clock frequency increases ...

  • Page 15

    ... AD9280 in the external reference mode. The external reference input for the AD876-8 will now be placed on the reference pins of the AD9280. The clamp controls will be grounded by the AD876-8 socket. The AD9280 has a 3 clock cycle delay compared to a 3.5 cycle delay of the AD876- ...

  • Page 16

    ... AD9280’s baseband region. Also, it reduces any out-of-band noise which would also be aliased back due to the AD9280’s noise band- width of 220+ MHz. Note, the bandpass filters specifications are application dependent and will affect both the total distor- tion and noise performance of this circuit ...

  • Page 17

    ... INPUT POWER LEVEL – dBFS Figure 36. SNR/SFDR for MHz REV referenced to dBc. The AD9280 was operated in the differen- tial mode (via transformer) with span. The analog sup- ply (AVDD) and the digital supply (DRVDD) were set and 3.3 V, respectively. ...

  • Page 18

    ... BIT6 BIT7 REFBF REFBF 25 REFBS REFBS 26 VREF VREF 27 AIN AIN + AVSS DRVSS C33 10/10V 14 1 NOTE: THE AD9280 IS EXERCISED IN AN AD9200 EVALUATION BOARD R11 +3–5A 15k AD822 5 R15 0.1 F C11 0.1 F +3–5A R13 11k R12 C29 ...

  • Page 19

    ... TP10 R3 DCIN 100 +3–5D C31 10/10V DRVDD C23 10/10V 14 74AHC14 PWR U6 AVDD GND C25 7 33/16V +3–5A C27 10/10V Figure 39b. Evaluation Board Schematic –19– AD9280 JP14 AVDD R5 MODE 10k JP15 R6 10k JP16 GND AVDDCLK R35 4.99k R34 ...

  • Page 20

    ... AD9280 Figure 40a. Evaluation Board, Component Signal (Not to Scale) Figure 40b. Evaluation Board, Solder Signal (Not to Scale) –20– REV. E ...

  • Page 21

    ... Figure 40c. Evaluation Board Power Plane (Not to Scale) Figure 40d. Evaluation Board Ground Plane (Not to Scale) REV. E –21– AD9280 ...

  • Page 22

    ... AD9280 Figure 40e. Evaluation Board Component Silk (Not to Scale) Figure 40f. Evaluation Board Solder Silk (Not to Scale) C33 C6 C18 C19 C16 C17 –22– REV. E ...

  • Page 23

    ... DRVDD = all cases, check your logic family data sheets for compatibility with the AD9280 Digital Specification table. THREE-STATE OUTPUTS The digital outputs of the AD9280 can be placed in a high impedance state by setting the THREE-STATE pin to HIGH. This feature is provided to facilitate in-circuit testing or evaluation. ...

  • Page 24

    ... Model Temperature Range AD9280ARS −40°C to +85°C AD9280ARSRL −40°C to +85°C AD9280ARSZ −40°C to +85°C AD9280ARSZRL −40°C to +85°C AD9280- RoHS Compliant Part Shrink Small Outline. REVISION HISTORY 8/10—Rev Rev. E Changes to Pin Configuration and Pin Function Descriptions .. 5 Updated Outline Dimensions ...