AD7721 Analog Devices, AD7721 Datasheet - Page 3

• Manufacturer Part Number: AD7721
• Description: CMOS, 12-/16-Bit, 312.5 kHz/468.75 kHz Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7721

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: n/a
• Interface: Par,Ser
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

REV. A
SPECIFICATIONS
Parameter
PARALLEL MODE ONLY
STATIC PERFORMANCE
ANALOG INPUTS
REFERENCE INPUTS
DYNAMIC SPECIFICATIONS
CLOCK
LOGIC INPUTS
LOGIC OUTPUTS
POWER SUPPLIES
NOTES
1
2
3
Specifications subject to change without notice.
Operating temperature range is as follows: A Version: –40 C to +85 C; S Version: –55 C to +125 C.
Applies after calibration at temperature of interest.
Full-scale error applies to both positive and negative full-scale error. The ADC gain is calibrated w.r.t. the voltage on the REFIN pin.
Resolution
Minimum Resolution for Which
No Missing Codes Is Guaranteed
Differential Nonlinearity
Integral Nonlinearity
DC CMRR
Offset Error
Full-Scale Error
Unipolar Offset Drift
Bipolar Offset Drift
Signal Input Span (VIN1–VIN2):
Maximum Input Voltage
Minimum Input Voltage
Input Sampling Capacitance
Input Sampling Rate
Differential Input Impedance
V
REFIN Input Current
Signal to (Noise + Distortion)
Total Harmonic Distortion
Frequency Response
0 kHz–140 kHz
152.8 kHz
172.67 kHz to 9.827 MHz
CLK Duty Ratio
V
V
V
V
I
C
V
V
AV
DV
I
Power Consumption
Power Consumption
INH
DD
REFIN
CLKH
CLKL
INH
INL
OH
OL
IN
Unipolar Mode
Bipolar Mode
Unipolar Mode
Bipolar Mode
Bipolar Mode
Unipolar Mode
DD
DD
, Input Capacitance
(Total from AV
, Input Current
, Output High Voltage
, Output Low Voltage
, Input Low Voltage
, Input High Voltage
, CLK Low Voltage
, CLK High Voltage
2
2, 3
DD
, DV
DD
)
1
(AV
REFIN = +2.5 V; T
DD
A Version
12
12
70
0.04
0.035
0 to V
AV
0
1.6
2 f
31.25
2.4 to 2.6
200
70
–78
–3
–72
45 to 55
0.7
0.3
2.0
0.8
10
10
4.0
0.4
4.75/5.25
4.75/5.25
28.5
150
100
= +5 V
1/2
1/2
3.66
3.66
4.88
4.88
V
0.05
CLK
REFIN
DD
DV
DV
REFIN
/2
DD
DD
5%; DV
A
= T
MIN
DD
to T
= +5 V
12
1.6
2.0
0.8
4.0
0.4
4.75/5.25
4.75/5.25
S Version
12
70
0.04
0.035
0 to V
AV
0
2 f
31.25
2.4 to 2.6
200
70
–78
–3
–72
45 to 55
0.7
0.3
10
10
28.5
150
100
1/2
1/2
3.66
3.66
4.88
4.88
V
0.05
MAX
CLK
–3–
REFIN
DD
, unless otherwise noted)
DV
DV
REFIN
/2
5%; AGND = DGND = 0 V, f
DD
DD
Bits
Bits min
LSB typ
LSB typ
dB min
mV max
mV max
mV max
mV max
mV/ C typ
mV/ C typ
Volts max
Volts max
Volts
Volts
pF typ
MHz
k typ
V min/V max
dB min
dB max
dB max
dB min
V min
V max
V min
V max
pF max
V min
V max
V min/V max
V min/V max
mA max
mW max
Units
dB min
% max
A typ
A max
W max
CLK
12-Bit Operation
Typically 0.61 mV
Typically 0.61 mV
Typically 0.61 mV
Typically 1.22 mV
Guaranteed by Design
With 10 MHz on CLK Pin
|I
|I
Active Mode
Test Conditions/Comments
Guaranteed 12 Bits Monotonic
Bipolar Mode
UNI = V
UNI = V
Input Bandwidth 0 kHz to 140 kHz
Input Bandwidth 0 kHz to 152.8 kHz
For Specified Operation
CLK Uses CMOS Logic
Digital Inputs Equal to 0 V or DV
Standby Mode
OUT
OUT
= 10 MHz,
|
|
IH
IL
200 A
1.6 mA
AD7721
DD