AD7859 Analog Devices, AD7859 Datasheet - Page 23

• Manufacturer Part Number: AD7859
• Description: 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit, Parallel Sampling ADCs
• Manufacturer: Analog Devices

Specifications of AD7859

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: LCC,QFP

REV. A
System Gain and Offset Interaction
The architecture of the AD7859/AD7859L leads to an interac-
tion between the system offset and gain errors when a system
calibration is performed. Therefore, it is recommended to per-
form the cycle of a system offset calibration followed by a sys-
tem gain calibration twice. When a system offset calibration is
performed, the system offset error is reduced to zero. If this is
followed by a system gain calibration, then the system gain error
is now zero, but the system offset error is no longer zero. A sec-
ond sequence of system offset error calibration followed by a
system gain calibration is necessary to reduce system offset error
to below the 12-bit level. The advantage of doing separate
system offset and system gain calibrations is that the user has
more control over when the analog inputs need to be at the
required levels, and the CONVST signal does not have to be
used.
Alternatively, a system (gain + offset) calibration can be per-
formed. At the end of one system (gain + offset) calibration, the
system offset error is zero, while the system gain error is reduced
from its initial value. Three system (gain + offset) calibrations
are required to reduce the system gain error to below the 12-bit
error level. There is never any need to perform more than three
system (gain + offset) calibrations.
In bipolar mode the midscale error is adjusted for an offset cali-
bration and the positive full-scale error is adjusted for the gain
calibration; in unipolar mode the zero-scale error is adjusted for
an offset calibration and the positive full-scale error is adjusted
for a gain calibration.
System Calibration Timing
The timing diagram in Figure 33 is for a software full system
calibration. It may be easier in some applications to perform
separate gain and offset calibrations so that the CONVST bit in
the control register does not have to be programmed in the
middle of the system calibration sequence. Once the write to the
control register setting the bits for a full system calibration is
completed, calibration of the internal DAC is initiated and the
BUSY line goes high. The full-scale system voltage should be
applied to the analog input pins, AIN(+) and AIN(–) at the start
of calibration. The BUSY line goes low once the DAC and sys-
tem gain calibration are complete. Next the system offset volt-
age should be applied across the AIN(+) and AIN(–) pins for a
minimum setup time (t
CS. This second write to the control register sets the CONVST
bit to 1 and at the end of this write operation the BUSY signal is
triggered high (note that a CONVST pulse can be applied in-
stead of this second write to the control register). The BUSY
signal is low after a time t
section is complete. The full system calibration is now complete.
SETUP
CAL2
) of 100 ns before the rising edge of
when the system offset calibration
–23–
The timing for a system (gain + offset) calibration is very similar
to that of Figure 33, the only difference being that the time
t
ternal DAC is not calibrated. The BUSY signal signifies when
the gain calibration is finished and when the part is ready for the
offset calibration.
The timing diagram for a system offset or system gain calibra-
tion is shown in Figure 34. Here again a write to the control reg-
ister initiates the calibration sequence. At the end of the control
register write operation the BUSY line goes high and it stays
high until the calibration sequence is finished. The analog input
should be set at the correct level for a minimum setup time
(t
rect level until the BUSY signal goes low.
CAL1
BUSY
DATA
SETUP
Figure 33. Timing Diagram for Full System Calibration
WR
AIN
CS
DATA
BUSY
Figure 34. Timing Diagram for System Gain or
System Offset Calibration
WR
AIN
CS
is replaced by a shorter time of the order of t
) of 100 ns before the CS rising edge and stay at the cor-
HI-Z
VALID
DATA
HI-Z
V
SYSTEM FULL SCALE
t
19
HI-Z
t
SETUP
t
DATA LATCHED INTO
CONTROL REGISTER
CAL1
VALID
DATA
t
AD7859/AD7859L
19
t
V
SETUP
SYSTEM FULL SCALE
HI-Z
HI-Z
DATA LATCHED INTO
CONTROL REGISTER
VALID
DATA
t
CAL2
t
CONVST BIT SET TO 1 IN
CONTROL REGISTER
19
OR V
V
OFFSET
CAL2
t
CAL2
OFFSET
as the in-