AD7859 Analog Devices, AD7859 Datasheet - Page 9

• Manufacturer Part Number: AD7859
• Description: 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit, Parallel Sampling ADCs
• Manufacturer: Analog Devices

Specifications of AD7859

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: LCC,QFP

REV. A
CONTROL REGISTER
The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described
below. The power-up status of all bits is 0.
Bit
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mnemonic
SGL/DIFF
CHSLT2
CHSLT1
CHSLT0
PMGT1
PMGT0
RDSLT1
RDSLT0
AMODE
CONVST
CALMD
CALSLT1
CALSLT0
STCAL
SGL/DIFF
RDSLT0
MSB
tion configures the input channels in single ended mode. Please see Table III for channel selection.
channel selection information.
When SGL/DIFF is 0, AMODE selects between unipolar and bipolar analog input ranges. A logic 0 in
this bit position selects the unipolar range, 0 to V
this bit position selects the bipolar range –V
+V
swing from 0 V to +V
cuitry. If AMODE is a 0, AGND is selected. If AMODE is a 1, then AIN8 is selected. Please see
Table III for more information.
reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration (see
calibration section on page 21).
mine the type of calibration performed by the part (see Table IV).
With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see Table V for more details).
CALMD, CALSLT1 and CALSLT0 bits. Please see Table IV. When STCAL is set to a zero, no cali-
bration is performed.
These three bits are used to select the analog input on which the conversion is performed. The analog
inputs can be configured as eight single-ended channels or four pseudo-differential channels. The
default selection is AIN1 for the positive input and AIN2 for the negative input. Please see Table III for
Power-Down modes (See Power-Down section for more details).
Theses two bits determine which register is addressed for the read operations. Please see Table II.
Conversion Start Bit. A logic 1 in this bit position starts a single conversion, and this bit is automatically
Calibration Selection Bits 1 and 0. These bits have two functions, depending on the STCAL bit.
With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits, along with the CALMD bit, deter-
Comment
A 0 in this bit position configures the input channels for pseudo-differential mode. A 1 in this bit posi-
Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various
Analog Mode Bit. This bit has two different functions, depending on the status of the SGL/DIFF bit.
When SGL/DIFF is 1, AMODE selects the source for the AIN(–) channel of the sample and hold cir-
Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table IV).
Start Calibration Bit. When STCAL is set to a 1, a calibration is performed, as determined by the
REF
CHSLT2
AMODE
/2). In this case AIN(–) needs to be tied to at least +V
CONTROL REGISTER BIT FUNCTION DESCRIPTION
CHSLT1
CONVST
REF
.
CHSLT0
CALMD
–9–
REF
CALSLT1
/2 to +V
PMGT1
REF
(i.e., AIN(+) – AIN(–) = 0 to V
REF
/2 (i.e., AIN(+) – AIN(–) = –V
REF
CALSLT0
PMGT0
/2 to allow AIN(+) to have a full input
AD7859/AD7859L
RDSLT1
STCAL
LSB
REF
). A logic 1 in
REF
/2 to