AD7715 Analog Devices, AD7715 Datasheet - Page 15

• Manufacturer Part Number: AD7715
• Manufacturer: Analog Devices

Specifications of AD7715

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 19.2kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (Vref/PGA Gain) p-p,Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC,SOP

Table 13.
MD1
0
0
1
1
Table 14. Output Update Rates
CLK
0
0
0
0
1
1
1
1
1
TEST REGISTER (RS1, RS0 = 1, 0)
The part contains a test register, which is used in testing the
device. The user is advised not to change the status of any of the
bits in this register from the default (power-on or reset) status
of all 0s as the part will be placed in one of its test modes and
will not operate correctly. If the part enters one of its test modes,
exercising RESET will exit the part from the mode. An alterna-
tive scheme for getting the part out of one of its test modes, is to
reset the interface by writing 32 successive 1s to the part and
then load all 0s to the test register.
Assumes correct clock frequency at MCLK IN pin.
1
MD0
0
1
0
1
Operating Mode
Normal mode. This operating mode is the default mode of operation of the device whereby the device is performing normal
conversions. The AD7705 is placed in this mode after power-on or reset.
Self-calibration. This is a one step calibration sequence and when complete the part returns to normal mode with MD1 and
MD0 returning to 0, 0. The DRDY output or DRDY bit goes high when calibration is initiated and returns low when this self-
calibration is complete and a new valid word is available in the data register. The zero-scale calibration is performed at the
selected gain on internally shorted (zeroed) inputs and the full-scale calibration is performed at the selected gain on an
internally generated V
Zero-scale system calibration. Zero-scale system calibration is performed at the selected gain on the input voltage provided
at the analog input during this calibration sequence. This input voltage should remain stable for the duration of the
calibration. The DRDY output or DRDY bit goes high when calibration is initiated and returns low when this zero-scale
calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to
normal mode with MD1 and MD0 returning to 0, 0.
Full-scale system calibration. Full-scale system calibration is performed at the selected gain on the input voltage provided at
the analog input during this calibration sequence. This input voltage should remain stable for the duration of the
calibration. The DRDY output or DRDY bit goes high when calibration is initiated and returns low when this full-scale
calibration is complete and a new valid word is available in the data register. At the end of the calibration, the part returns to
normal mode with MD1 and MD0 returning to 0, 0.
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
REF
/selected gain.
Output Update Rate
20 Hz
25 Hz
100 Hz
200 Hz
50 Hz
60 Hz
250 Hz
500 Hz
Rev. D | Page 15 of 40
DATA REGISTER (RS1, RS0 = 1, 1)
The data register on the part is a read-only 16-bit register
that contains the most up-to-date conversion result from the
AD7715. If the communications register data sets up the part
for a write operation to this register, a write operation must
actually take place to return the part to where it is expecting
a write operation to the communications register (the default
state of the interface). However, the 16 bits of data written to
the part will be ignored by the AD7715.
−3 dB Filter Cutoff
5.24 Hz
6.55 Hz
26.2 Hz
52.4 Hz
13.1 Hz
15.7 Hz (default status)
65.5 Hz
131 Hz
AD7715