AD5755 Analog Devices, AD5755 Datasheet
AD5755
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AD5755 Summary of contents
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... On-chip reference (±10 ppm/°C maximum) −40°C to +105°C temperature range APPLICATIONS Process control Actuator control PLCs GENERAL DESCRIPTION The AD5755 is a quad, voltage and current output DAC that operates with a power supply range from −26 + –15V AGND DV ...
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... Pin Configuration and Function Descriptions........................... 13 Typical Performance Characteristics ........................................... 16 Voltage Outputs .......................................................................... 16 Current Outputs ......................................................................... 20 DC-to-DC Block......................................................................... 24 Reference ..................................................................................... 25 General......................................................................................... 26 Terminology .................................................................................... 27 Theory of Operation ...................................................................... 29 DAC Architecture....................................................................... 29 Power-On State of AD5755....................................................... 29 Serial Interface ............................................................................ 30 Transfer Function ....................................................................... 30 Registers ........................................................................................... 31 Programming Sequence to Write/Enable the Output Correctly ...................................................................................... 32 Changing and Reprogramming the Range ............................. 32 Data Registers ............................................................................. 33 ...
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... Changes to Readback Operation Section and changes to Table 26.............................................................................................38 Changes to Voltage Output Short-Circuit Protection Section..40 Changes to Figure 78 ......................................................................41 Changes to Figure 81 through Figure 84 Captions.....................44 Changes to Transient Voltage Protection Section and changes to Figure 85...........................................................................................47 Changes to Galvanically Isolated Interface Section....................48 5/11—Revision 0: Initial Version Rev Page AD5755 ...
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... SYNC SDO GAIN REG A FAULT OFFSET REG A STATUS REGISTER WATCHDOG ALERT TIMER (SPI ACTIVITY) REFOUT VREF REFERENCE DAC CHANNEL A REFIN BUFFERS DAC CHANNEL B AD1 AD5755 DAC CHANNEL C DAC CHANNEL D AD0 SW POWER 7.4V TO 29.5V CONTROL R2 16 DAC + DAC A REG A R1 VOUT RANGE SCALING ...
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... V 20 ppm FSR 12/6 16 kΩ μF 0.06 Ω 50 μV/V Rev Page AD5755 = 300 Ω; all specifications MIN Test Conditions/Comments AV = −15 V, loaded and unloaded 25° 25°C A Drift after 1000 hours 150° ±5 V, ±10 V ranges ...
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... AD5755 1 Parameter DC Crosstalk CURRENT OUTPUT Output Current Ranges Resolution ACCURACY (EXTERNAL R ) SET Total Unadjusted Error (TUE) B Version A Version TUE Long-Term Stability Relative Accuracy (INL) Differential Nonlinearity (DNL) −1 Offset Error 2 Offset Error Drift Gain Error 2 Gain TC Full-Scale Error 2 Full-Scale TC DC Crosstalk ...
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... −26.4 −10.8 V 2.7 5.5 V Rev Page AD5755 Test Conditions/Comments The dc-to-dc converter has been characterized with a maximum load of 1 kΩ, chosen such that compliance is not exceeded; see Figure 52 and DC-DC MaxV bits in Table 25 For specified performance T = 25° kHz Drift after 1000 hours 150° ...
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... AD5755 1 Parameter BOOST Power Dissipation 1 Temperature range: −40°C to +105°C; typical at +25°C. 2 Guaranteed by design and characterization; not production tested. 3 For current outputs with internal R , the offset, full-scale, and TUE measurements exclude dc crosstalk. The measurements are made with all four channels enabled SET loaded with the same code ...
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... SYNC high to next SYNC low (digital slew rate control enabled) (all DACs updated) μs min SYNC high to next SYNC low (digital slew rate control disabled) (single DAC updated) ) and timed from a voltage level of 1 Rev Page AD5755 = 300 Ω; all specifications MIN MAX Figure unless ...
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... AD5755 Timing Diagrams SCLK SYNC t 7 SDIN MSB LDAC V OUT_x LDAC = 0 V OUT_x CLEAR V OUT_x RESET SCLK 1 SYNC MSB SDIN INPUT WORD SPECIFIES REGISTER TO BE READ SDO UNDEFINED LSB ...
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... SDO DISABLED X X D15 D14 SDO_ STATUS STATUS ENAB Figure 5. Status Readback During Write 200µ (MIN OUTPUT OH PIN V (MAX 50pF 200µ Figure 6. Load Circuit for SDO Timing Diagram Rev Page AD5755 MSB STATUS STATUS ...
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... AD5755 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents 100 mA do not cause SCR latch-up. Table 4. Parameter Rating AGND, DGND −0 + BOOST_x AV to AGND, DGND +0 − −0 + AGND − ...
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... Scale) SDO LDAC PIN, OR, ALTERNATIVELY, IT CAN BE LEFT ELECTRICALLY UNCONNECTED. Figure 7. Pin Configuration Figure 3 ). Using this mode, all analog outputs can be updated simultaneously. The Rev Page AD5755 48 COMP DCDC_C 47 I OUT_C 46 V BOOST_C ...
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... AD5755 Pin No. Mnemonic Description 15 ALERT Active High Output. This pin is asserted when there has been no SPI activity on the interface pins for a predetermined time. See the Device Features section for more information. 16 FAULT Active Low Output. This pin is asserted low when an open circuit in current mode is detected, a short circuit in voltage mode is detected, a PEC error is detected overtemperature is detected (see the Device Features section) ...
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... Note that the addition of this capacitor OUT_C Output Buffer. Connecting a 220 pF capacitor between OUT_D pin allows the voltage output to drive μF. Note that the addition of this capacitor OUT_D Rev Page AD5755 stage, which is OUT_x . OUT_C . This pin must stay within ±3.0 V OUT_C ...
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... AD5755 TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUTS 0.0015 ±10V RANGE ±5V RANGE +10V RANGE +5V RANGE 0.0010 +10V RANGE WITH DCDC 0.0005 0 –0.0005 –0.0010 0 10k 20k 30k 40k CODE Figure 8. Integral Nonlinearity Error vs. DAC Code 1.0 ±10V RANGE AV DD 0.8 ±5V RANGE AV SS ...
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... OUTPUT UNLOADED –40 – TEMPERATURE (°C) Figure 18. Zero-Scale Error vs. Temperature 0V TO 10V RANGE MAX INL 0V TO 10V RANGE MIN INL 25° –26.4V FOR AV > +26. SUPPLY (V) Figure 19. Integral Nonlinearity Error vs. AV /|AV DD AD5755 80 100 80 100 ...
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... AD5755 1 +15V –15V 0.8 SS ALL RANGES 0 25° –26.4V FOR AV > +26. 0.4 0.2 DNL ERROR MAX 0 DNL ERROR MIN –0.2 –0.4 –0.6 –0.8 –1 SUPPLY (V) Figure 20. Differential Nonlinearity Error vs. AV 0.008 0V TO 10V RANGE MAX INL 0V TO 10V RANGE MIN INL T = 25° ...
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... POC = +15V –15V SS ±10V RANGE T = 25°C A INT_ENABLE = TIME (µs) Figure 29. V vs. Time on Output Enable OUT_x +15V +15V BOOST AV = –15V 25° 100 1k 10k 100k FREQUENCY (Hz) Figure 30. V PSRR vs. Frequency OUT_x AD5755 10M ...
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... AD5755 CURRENT OUTPUTS 0.0025 AV = +15V –15V 25°C A 0.0015 0.0005 –0.0005 –0.0015 4mA TO 20mA, EXTERNAL R SET 4mA TO 20mA, EXTERNAL R SET , WITH DC-TO-DC CONVERTER 4mA TO 20mA, INTERNAL R SET 4mA TO 20mA, INTERNAL R SET , WITH DC-TO-DC CONVERTER –0.0025 0 10000 20000 30000 40000 CODE Figure 31 ...
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... SET 0 4mA TO 20mA RANGE MAX INL 4mA TO 20mA RANGE MIN INL T = 25° –26.4V FOR AV > +26. SUPPLY (V) Figure 42. Integral Nonlinearity Error vs Over Supply, Internal R SET AD5755 SET SET SET SET SET SET 80 100 ...
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... AD5755 1.0 ALL RANGES 0.8 INTERNAL AND EXTERNAL R SET T = 25° –15V FOR AV > +26. 0.4 0.2 DNL ERROR MAX 0 DNL ERROR MIN –0.2 –0.4 –0.6 –0.8 –1 SUPPLY (V) Figure 43. Differential Nonlinearity Error vs. AV 0.012 0.010 0.008 0.006 0.004 4mA TO 20mA RANGE MAX TUE 4mA TO 20mA RANGE MIN TUE 0 ...
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... LOAD f = 410kHz SW INDUCTOR = 10µH (XAL4040-103 25° CURRENT (mA +15V +15V BOOST – –15V 25°C A –40 –60 –80 –100 –120 10 100 1k 10k 100k FREQUENCY (Hz) Figure 53. I PSRR vs. Frequency OUT_x AD5755 20 1M 10M ...
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... AD5755 DC-TO-DC BLOCK 4. 5. 0mA TO 24mA RANGE 1kΩ LOAD 60 EXTERNAL 410kHz SW 55 INDUCTOR = 10µH (XAL4040-103 25° CURRENT (mA) Figure 54. Efficiency at V vs. Output Current (See Figure 78) BOOST_x 90 20mA 0mA TO 24mA RANGE 1kΩ LOAD ...
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... Figure 62. REFOUT vs. Temperature (When the AD5755 is soldered onto a PCB, the reference shifts due to thermal shock on the package. The average output voltage shift is −4 mV. Measurement of these parts after seven days shows that the outputs typically shift back 2 mV toward their initial values. ...
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... AD5755 GENERAL 450 400 350 300 250 200 150 100 SDIN VOLTAGE (V) Figure 65. DI vs. Logic Input Voltage 25° OUT 0 OUTPUT UNLOADED –2 –4 –6 –8 –10 – VOLTAGE (V) Figure 66. AI /AI vs ...
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... V/μs. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5755 is powered on specified as the area of the glitch in nV-sec. See Figure 28 and Figure 46. Digital-to-Analog Glitch Impulse ...
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... AD5755 Glitch Impulse Peak Amplitude Glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the DAC register changes state specified as the amplitude of the glitch in mV and is measured when the digital input code is changed by 1 LSB at the major carry transition (~0x7FFF to 0x8000) ...
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... This input voltage is then buffered before it is applied to the DAC. POWER-ON STATE OF AD5755 +V SENSE_X On initial power-up of the AD5755, the power-on reset circuit powers state that is dependent on the power-on V OUT_X condition (POC) pin. If POC = 0, the voltage output and current output channels power up in tristate mode. – ...
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... Figure 73. Simplified Serial Interface of Input Loading Circuitry TRANSFER FUNCTION Table 6 shows the input code to ideal output voltage relationship for the AD5755 for straight binary data coding of the ±10 V output range. Table 6. Ideal Output Voltage to Input Code Relationship Straight Binary Data Coding ...
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... Used to program offset trim per channel basis. AD5755 data bits = D15 to D0. There are four offset registers, one per DAC channel. Clear Code Register (×4) Used to program clear code on a per channel basis. AD5755 data bits = D15 to D0. There are four clear code registers, one per DAC channel. Control Main Control Register Used to configure the part for main operation ...
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... AD5755 PROGRAMMING SEQUENCE TO WRITE/ENABLE THE OUTPUT CORRECTLY To correctly write to and set up the part from a power-on condition, use the following sequence: 1. Perform a hardware or software reset after initial power-on. 2. The dc-to-dc converter supply block must be configured. Set the dc-to-dc switching frequency, maximum output voltage allowed, and the phase that the four dc-to-dc channels clock at ...
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... DUT_AD0 Table 9. Input Register Decode Bit Description R/W Indicates a read from or a write to the addressed register. DUT_AD1, DUT_AD0 Used in association with the external pins, AD1 and AD0, to determine which AD5755 device is being addressed by the system controller. DUT_AD1 DREG2, DREG1, DREG0 Selects whether a data register or a control register is written to ...
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... AD5755 Gain Register The 16-bit gain register, as shown in Table 11, allows the user to adjust the gain of each channel in steps of 1 LSB. This is done by setting the DREG[2:0] bits to 010 possible to write the same gain code to all four DAC channels at the same time by setting the DREG[2:0] bits to 011 ...
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... Software register D10 EWD WD1 WD0 X ShtCctLim Timeout Period (ms 100 200 pin in the event of a short-circuit condition. OUT_x Rev Page AD5755 LSB D15 D14 D13 D12 to D0 CREG2 CREG1 CREG0 Data LSB OUTEN_ALL DCDC_All X ...
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... AD5755 DAC Control Register The DAC control register is used to configure each DAC channel. The DAC control register options are shown in Table 20 and Table 21. Table 20. Programming DAC Control Register D15 D14 D13 D12 D11 D10 don’t care. ...
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... D11, in the status register also used as part of the watchdog feature when it is enabled. This feature is useful to ensure that communication has not been lost between the MCU and the AD5755 and that the datapath lines are working properly (that is, SDI, SCLK, and SYNC ). Table 22. Programming the Software Register ...
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... To read back the gain register of Device 1, Channel A on the AD5755, implement the following sequence: 1. Write 0xA80000 to the AD5755 input register. This configures the AD5755 Device Address 1 for read mode with the gain register of Channel A selected. All the data bits, D15 to D0, are don’t cares. 2. ...
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... Ramp Active This bit is set while any one of the output channels is slewing (slew rate control is enabled on at least one channel). Over TEMP This bit is set if the AD5755 core temperature exceeds approximately 150°C. V Fault This bit is set if a fault is detected on the V ...
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... AD5755 DEVICE FEATURES OUTPUT FAULT The AD5755 is equipped with a FAULT pin, an active low open- drain output allowing several AD5755 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault scenarios: • ...
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... Table 18 and Table 19). OUTPUT ALERT The AD5755 is equipped with an ALERT pin. This is an active high CMOS output. The AD5755 also has an internal watchdog timer. When enabled, it monitors SPI communications. If 0x195 is not received by the software register within the timeout period, the ALERT pin goes active ...
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... AD5755 DIGITAL SLEW RATE CONTROL The slew rate control feature of the AD5755 allows the user to control the rate at which the output value changes. This feature is available on both the current and voltage outputs. With the slew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load ...
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... DC-to-DC Converter Operation The on-board dc-to-dc converters use a constant frequency, peak current mode control scheme to step 4 5 drive the AD5755 output channel. These are designed to operate in discontinuous conduction mode (DCM) with a duty cycle of <90% typical. Discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. The dc-to-dc converters are nonsynchronous ...
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... The input capacitor provides much of the dynamic current required for the dc-to-dc converter and should be a low ESR component. For the AD5755, a low ESR tantalum or ceramic capacitor of 10 μF is recommended for typical applications. Ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature ...
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... Rev Page 0mA TO 24mA RANGE 1kΩ LOAD f = 410kHz SW INDUCTOR = 10µH (XAL4040-103 25° OUT V BOOST TIME (ms) Current vs. Time for 24 mA Step Through 1 kΩ Load CC with Slew Rate Control AD5755 supplies ...
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... APPLICATIONS INFORMATION VOLTAGE AND CURRENT OUTPUT RANGES ON THE SAME TERMINAL When using a channel of the AD5755, the current and voltage output pins can be connected to two separate terminals or tied together and connected to a single terminal. There is no conflict with tying the two output pins together because only the voltage output or the current output can be enabled at any one time ...
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... Layout—Traces The power supply lines of the AD5755 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to prevent radiating noise to other parts of the board and should never be run near the reference inputs ...
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... The Analog Devices iCoupler® products can provide voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5755 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 86 shows a 4- channel isolated interface to the AD5755 using an ADuM1400 ...
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... Rev Page PIN 1 INDICATOR 64 1 7.25 EXPOSED PAD 7.10 SQ (BOTTOM VIEW) 6. 0.25 MIN 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Description Package Option 64-lead LFCSP_VQ CP-64-3 64-lead LFCSP_VQ CP-64-3 Evaluation Board AD5755 ...
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... AD5755 NOTES Rev Page Data Sheet ...
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... Data Sheet NOTES Rev Page AD5755 ...
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... AD5755 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07304-0-11/11(A) Rev Page Data Sheet ...