AD9146 Analog Devices, AD9146 Datasheet
AD9146
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... Analog Devices. Trademarks and registered trademarks are the property of their respective owners. TxDAC+ Digital-to-Analog Converter The AD9146 TxDAC+® includes features optimized for direct conversion transmit applications, including complex digital mod- ulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature = 25 Ω ...
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... AD9146 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Companion Products ....................................................................... 1 Typical Signal Chain......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 Digital Specifications ................................................................... 6 Digital Input Data Timing Specifications ................................. 6 AC Specifications .......................................................................... 7 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ...
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... Data Sheet REVISION HISTORY 1/12—Rev Rev. A Change to General Description Section ......................................... 1 Change to DCI Delay[1:0], Table 11 ............................................. 23 Changes to Interface Timing Section, Figure 37, and Figure 38 ........................................................................................... 31 Changes to SED Operation Section and Table 26 ....................... 50 4/11—Revision 0: Initial Version Rev Page AD9146 ...
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... AD9146 FUNCTIONAL BLOCK DIAGRAM D7P/D7N f /2 DATA FIFO PRE HB1 MOD D0P/D0N DCI FRAME INTERNAL CLOCK TIMING AND CONTROL LOGIC PROGRAMMING SERIAL REGISTERS INPUT/OUTPUT PORT OFFSET 10 INV HB2 SINC Q OFFSET 16 16 PLL CONTROL DAC_CLK POWER-ON RESET PLL_LOCK MULTICHIP SYNC SYNCHRONIZATION Figure 2 ...
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... Guaranteed 20 0.04 100 30 1.2 5 3.13 3.3 1.71 1.8 1.71 1.8 780 864 8.5 260 −40 +25 Rev Page AD9146 Max Unit Bits LSB LSB +0.001 % FSR +3.6 % FSR 31.66 mA +0.3 % FSR/V +1.0 V MΩ ns ppm/°C ppm/°C ppm/°C V kΩ 3.47 V 1. ...
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... AD9146 DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX Table 2. Parameter CMOS INPUT LOGIC LEVEL Input V Logic High IN Input V Logic Low IN CMOS OUTPUT LOGIC LEVEL Output V Logic High OUT Output V Logic Low OUT LVDS RECEIVER INPUTS 1 Input Voltage Range ...
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... HB2 DAC 300 600 300 307.5 600 600 615 1200 150 300 150 153.75 300 300 307.5 600 AD9146 307.5 615 615 1230 153.75 307.5 307.5 615 ...
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... AD9146 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating AVDD33 to AVSS, EPAD, CVSS −0 +3.6 V DVDD18, CVDD18 to AVSS, EPAD, −0 +2.1 V CVSS AVSS to EPAD, CVSS −0 +0.3 V EPAD to AVSS, CVSS −0 +0.3 V CVSS to AVSS, EPAD −0 +0.3 V FSADJ, REFIO, IOUT1P, IOUT1N, −0 AVDD33 + 0.3 V ...
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... TOP VIEW (Not to Scale) DVDD18 8 D7P 9 D7N 10 D6P 11 D6N 12 (AVSS). THE EPAD PROVIDES AN ELECTRICAL, THERMAL, AND MECHANICAL CONNECTION TO THE BOARD. Figure 3. Pin Configuration Rev Page RESET 35 DVDD18 34 IRQ SCLK 31 SDIO 30 TXENABLE 29 DVDD18 28 D0N 27 D0P 26 D1N 25 D1P AD9146 ...
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... AD9146 Pin No. Mnemonic Description 28 D0N Data Bit 0 (LSB), Negative. 29 DVDD18 1.8 V Digital Supply. Supplies power to digital core and digital data ports. 30 TXENABLE Active High Transmit Path Enable (CMOS). A low level on this pin clamps the DAC outputs to midscale. 31 SDIO Serial Port Data Input/Output (CMOS). ...
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... MHz DATA OUT 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 START 1MHz #RES BW 10kHz VBW 10kHz SWEEP 9.63s (1001pts) Figure 9. Single-Tone Spectrum, 4× Interpolation 200 MSPS 151 MHz DATA OUT AD9146 350 400 STOP 600MHz STOP 800MHz ...
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... AD9146 –55 –60 –65 –70 2×, 300MSPS –75 –80 –85 –90 – 100 150 200 250 f (MHz) OUT Figure 10. IMD vs. f over f and Interpolation, OUT DATA Digital Scale = 0 dBFS –55 0dBFS –6dBFS –12dBFS –60 –18dBFS –65 –70 –75 –80 – ...
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... PLL OFF 4×, PLL ON –64 –66 –68 –70 –72 –74 –76 –78 – 120 160 200 240 280 320 360 400 440 480 f (MHz) OUT over Interpolation, First OUT Alternate Channel 245.76 MSPS, PLL Off and PLL On DATA AD9146 ...
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... AD9146 –60 2×, PLL OFF 2×, PLL ON –62 4×, PLL OFF 4×, PLL ON –64 –66 –68 –70 –72 –74 –76 –78 – 120 160 200 240 280 320 360 400 440 480 f (MHz) OUT Figure 21. Four-Carrier W-CDMA ACLR vs. f OUT Alternate Channel 245 ...
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... By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev Page AD9146 /2. Images that typically DATA (output data rate) can be greatly suppressed. DAC ...
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... AD9146 THEORY OF OPERATION High performance, small size, and low power consumption make the AD9146 a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband (SSB) transmitters. ...
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... Figure 27. Serial Port Interface Timing, LSB First t DCSB t SCLK t t PWH PWL INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 28. Timing Diagram for Serial Port Register Write t DV DATA BIT n DATA BIT n – 1 Figure 29. Timing Diagram for Serial Port Register Read AD9146 ...
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... AD9146 DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS Table 10. Device Configuration Register Map Addr (Hex) Register Name Bit 7 0x00 Comm SDIO 0x01 Power control Power down I DAC 0x02 Tx enable control 0x03 Data format Binary data format 0x04 Interrupt enable Enable PLL lock ...
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... Q Aux DAC[9:8] Reference Current[2:0] Capacitor value Compare Compare fail pass 0LSB 0MSB 0LSB 0MSB 1LSB 1MSB 1LSB 1MSB NLSB NMSB NLSB NMSB AD9146 Default 0xE4 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xF9 0x01 0x00 0x00 0xF9 ...
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... AD9146 Table 11. Device Configuration Register Descriptions Register Address Name (Hex) Bits Name Comm 0x00 7 SDIO 6 LSB_FIRST 5 Reset Power 0x01 7 Power down I DAC Control 6 Power down Q DAC 5 Power down data receiver 4 Power down auxiliary ADC 3 Power down auxiliary DACs and reference 2 Power down clocks ...
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... This latched signal is automatically cleared when eight valid I/Q data pairs are received indicates that the SED logic detected an invalid input data pattern compared against the preprogrammed expected values. This is a latched signal. Rev Page AD9146 Default ...
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... AD9146 Register Address Name (Hex) Bits Name Clock 0x08 7 DACCLK duty correction Receiver 6 REFCLK duty correction Control 5 DACCLK cross-correction 4 REFCLK cross-correction PLL 0x0A 7 PLL enable Control 6 PLL manual enable [5:0] Manual VCO Band[5:0] 0x0C [7:6] PLL Loop Bandwidth[1:0] [4:0] PLL Charge Pump Current[4:0] 0x0D ...
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... These bits control the delay applied to the DCI signal. The DCI delay affects the sampling interval of the DCI with respect to the Dx inputs. See Table 14 165 ps delay of DCI signal 375 ps delay of DCI signal 615 ps delay of DCI signal 720 ps delay of DCI signal. Rev Page AD9146 Default 000 000000 N/A ...
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... AD9146 Register Address Name (Hex) Bits Name FIFO Control 0x17 [2:0] FIFO Phase Offset[2:0] FIFO Status 0x18 7 FIFO Warning 1 6 FIFO Warning 2 2 FIFO soft align acknowledge 1 FIFO soft align request 0x19 [7:0] FIFO Level[7:0] Datapath 0x1B 7 Bypass premod Control 6 Bypass sinc 5 Set to 1 ...
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... FS Adjust Description Set this bit to 1 for proper operation. (The default value must be changed from 0 to 1.) This register identifies the device as an AD9146. See Register 0x39. I Phase Adj[9:0] is used to insert a phase offset between the I and Q datapaths. This offset can be used to correct for phase imbalance in a quadrature modulator ...
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... AD9146 Register Address Name (Hex) Bits Name Q DAC 0x45 7 Q DAC sleep Control [1:0] Q DAC FS Adj[9:8] Q Aux DAC 0x46 [7:0] Q Aux DAC[7:0] Data Q Aux DAC 0x47 7 Q aux DAC sign Control 6 Q aux DAC current direction 5 Q aux DAC sleep [1:0] Q Aux DAC[9:8] Die Temp ...
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... NLSB NLSB error. Errors Detected Q indicates which bits were received in NMSB NMSB error. This value corresponds to the die revision number. 0011 = Die Revision 1. Rev Page AD9146 Default 10110110 01111010 01000101 11101010 00010110 00011010 11000110 10101010 00000000 00000000 ...
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... AD9146 LVDS INPUT DATA PORTS The AD9146 has one LVDS data port that receives data for both the I and Q transmit paths. The device can accept data in byte and nibble formats. In byte and nibble modes, the data is sent over 8-bit and 4-bit LVDS data buses, respectively. The pin assignments of the bus in each mode are shown in Table 12 ...
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... FIFO pipeline delay and is part of the overall latency of the AD9146. Resetting the FIFO When the AD9146 is powered on, the FIFO depth is unknown. To avoid a concurrent read and write to the same FIFO address and to ensure a fixed pipeline delay important to reset the FIFO pointers to known states ...
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... The synchronization signal is sampled by the DAC clock in the AD9146. The edge of the DAC clock used to sample the synchronization signal is selected by Bit 3 of Register 0x10. The FRAME signal is used to reset the FIFO write pointer. In ...
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... Figure 38. Timing Diagram for Input Data Port (Bypass DCI Delay Mode) 0.88 The data interface timing can be verified using the sample error detection (SED) circuitry. See the Interface Timing Validation section for more information. Rev Page 0. 0. DVW KOW t H AD9146 ...
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... AD9146 DIGITAL DATAPATH The block diagram in Figure 39 shows the functionality of the digital datapath. The digital processing includes a premodula- tion block, two half-band (HB) interpolation filters, phase and offset adjustment blocks, and an inverse sinc filter. PHASE AND PREMOD HB1 HB2 OFFSET ADJUSTMENT Figure 39. Block Diagram of Digital Datapath The digital datapath accepts I and Q data streams and processes them as a quadrature data stream ...
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... IN2 Figure 43. HB2, Odd Filter Modes f f Input Data CENTER MOD DC None Real or complex f /4 None Complex None Complex None Complex Real or complex Complex Complex Complex IN IN AD9146 MODE 7 1.6 1.8 2 IN2 ...
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... DATAPATH CONFIGURATION Configuring the AD9146 datapath starts with the application requirements of the input data rate, the interpolation ratio, the output signal bandwidth, and the output signal center frequency. Given these four parameters, the first step in configuring the datapath is to verify that the device supports the bandwidth requirements ...
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... This 0x0000 Rev Page and I OUTxP are complementary current outputs, the sum always 20 mA. 0x4000 0x8000 0xC000 DAC OFFSET VALUE Figure 45. DAC Output Currents vs. DAC Offset Value AD9146 currents OUTxN OUTxP OUTxP 0xFFFF ...
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... AD9146 INVERSE SINC FILTER The inverse sinc (sinc −1 ) filter is a nine-tap FIR filter. The composite response of the sinc −1 filter and the sin(x)/x response of the DAC is shown in Figure 46. The composite response has a pass-band ripple of less than ±0. frequency of 0.4 × f ...
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... Data Sheet DAC INPUT CLOCK CONFIGURATIONS The AD9146 DAC sampling clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying uses the on-chip phase-locked loop (PLL), which accepts a reference clock operating at a submultiple of the desired DACCLK rate, most commonly the data input frequency. The PLL then multiplies ...
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... AD9146 PLL SETTINGS Three settings for the PLL circuitry should be programmed to their nominal values. The PLL values shown in Table 21 are the recommended settings for these parameters. Table 21. PLL Settings Register PLL Control Register Address PLL Loop Bandwidth[1:0] 0x0C PLL Charge Pump Current[4:0] ...
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... I I where DACCODE = Transmit DAC Output Configurations The optimum noise and distortion performance of the AD9146 is realized when it is configured for differential operation. The common-mode error sources of the DAC outputs are significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise ...
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... AUXILIARY DAC OPERATION OUTQ V – The AD9146 has two auxiliary DACs: one associated with the QN I path and one associated with the Q path. These auxiliary DACs can be used to compensate for dc offsets in the transmitted signal. Each auxiliary DAC has a single-ended current that can sink or source current into either the positive (P) or negative (N) out- put of the associated transmit DAC ...
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... RBQP 50Ω 38 IOUT2P Figure 56. Typical Interface Circuitry Between the AD9146 and the ADL537x Family of Modulators The baseband inputs of the ADL537x family require a dc bias of 500 mV. The nominal midscale output current on each output of the DAC (one-half the full-scale current). Therefore, a single 50 Ω ...
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... AD9146 REDUCING LO LEAKAGE AND UNWANTED SIDEBANDS Analog quadrature modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs, as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output. ...
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... PLL. The power dissipation of the PLL is typically 80 mA when enabled. Figure 59 through Figure 61 show the power dissipation of the AD9146 under a variety of operating conditions. All of the graphs were taken with data being supplied to both the I and Q DACs. The power consumption of the device does not vary significantly with changes in the coarse modulation mode selected or with the analog output frequency ...
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... TEMPERATURE SENSOR The AD9146 has a band gap temperature sensor for monitoring 6.611 µs the temperature change of the AD9146. The temperature must be calibrated against a known temperature to remove the part- to-part variation on the band gap circuit used to sense the temperature ...
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... PLL of each device is phase locked to it. The following procedure must be carried out on each individual device. Procedure for Synchronization When Using the PLL In the initialization of the AD9146, all the clock signals (DACCLK, DCI, FRAME, synchronization, and REFCLK) must be present and stable before the synchronization feature is turned on. Configure the AD9146 for data rate, periodic synchronization by writing 0xC8 to the sync control register (Register 0x10) ...
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... The following procedure must be carried out on each individual device. Procedure for Data Rate Synchronization When Directly Sourcing the DAC Sampling Clock Configure the AD9146 for data rate, periodic synchronization by writing 0xC8 to the sync control register (Register 0x10). = 800 MHz ...
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... Procedure for FIFO Rate Synchronization When Directly Sourcing the DAC Sampling Clock Configure the AD9146 for FIFO rate, periodic synchronization by writing 0x88 to the sync control register (Register 0x10). Addi- tional synchronization options are available (see the Additional Synchronization Features section). ...
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... AD9146 When these conditions are met, the outputs of the DACs are updated within one DAC clock cycle of each other. The timing requirements of the input signals are shown in Figure 67. t SKEW DACCLKP(1)/ DACCLKN(1) DACCLKP(2)/ DACCLKN( SUSYNC HSYNC REFCLKP(2)/ REFCLKN(2) DCIP(2)/ DCIN(2) ...
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... Data Sheet INTERRUPT REQUEST OPERATION The AD9146 provides an interrupt request output signal on Pin 34 ( IRQ ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. The IRQ pin is an open-drain, active low output. Pull the IRQ pin high external to the device ...
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... AD9146 INTERFACE TIMING VALIDATION The AD9146 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED circuitry compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port ...
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... Enabling the alignment of the I0 sample as described in the SED Operation section requires the use of the FRAME signal. The timing diagrams for byte and nibble modes are the same as during normal operation and are shown in Figure 33 and Figure 34, respectively. Rev Page AD9146 ...
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... AD9146 EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9146, certain sequences should be followed. This section shows an example start-up routine. This example uses the configuration described in the Device Configuration section. DEVICE CONFIGURATION The following device configuration is used for this example. • 122.88 MSPS DATA • ...
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... Dimensions shown in millimeters Package Description 48-lead LFCSP_WQ 48-lead LFCSP_WQ Evaluation Board Connected to ADL5375 Modulator Rev Page 5.65 PAD 5.60 SQ 5.55 13 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-48-13 CP-48-13 AD9146 ...
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... AD9146 NOTES Rev Page Data Sheet ...
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... Data Sheet NOTES Rev Page AD9146 ...
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... AD9146 NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09691-0-1/12(A) Rev Page Data Sheet ...