AD9146 Analog Devices, AD9146 Datasheet - Page 18

• Manufacturer Part Number: AD9146
• Description: Dual, 16-Bit, 1230 MSPS, TxDAC+® Digital-to-Analog Converter
• Manufacturer: Analog Devices

Specifications of AD9146

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Byte,LVDS,Nibble

AD9146
DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS
Table 10. Device Configuration Register Map
Addr
(Hex)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x0A
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x15
0x16
0x17
0x18
0x19
Register Name
Comm
Power control
Tx enable
control
Data format
Interrupt enable
Interrupt enable
Event flag
Event flag
Clock receiver
control
PLL control
PLL control
PLL control
PLL status
PLL status
Sync control
Sync control
Sync status
Sync status
Data receiver
status
DCI delay
FIFO control
FIFO status
FIFO status
PLL locked
FIFO
Warning 1
DACCLK
duty
correction
Bit 7
SDIO
Power
down
I DAC
Binary
data
format
Enable
PLL lock
lost
0
PLL lock
lost
PLL
enable
Sync
enable
Sync lost
Bandwidth[1:0]
PLL Loop
N2[1:0]
PLL manual
enable
Bit 6
LSB_FIRST
Power
down
Q DAC
Extended
delay
length
Q data
first
Enable
PLL
locked
0
PLL
locked
REFCLK
duty
correction
Data/FIFO
rate toggle
Sync
locked
FIFO
Warning 2
Bit 5
Reset
Power
down
data
receiver
Enable
extended
delay
MSB
swap
Enable
sync
signal lost
0
Sync
signal lost
DACCLK
cross-
correction
LVDS
FRAME
level high
Sync Phase Readback[7:0] (6.2 format)
Rev. A | Page 18 of 56
Power
down
voltage
reference
Sync signal
locked
Bit 4
Power
down
aux ADC
Enable
sync
signal
locked
Enable
AED
compare
pass
AED
compare
pass
REFCLK
cross-
correction
PLL cross-
control
enable
LVDS
FRAME
level low
FIFO Level[7:0]
Bit 3
Power
down aux
DACs and
reference
Power
down PLL
Enable
AED
compare
fail
AED
compare
fail
1
Rising
edge sync
LVDS DCI
level high
VCO Band Readback[5:0]
Sync Phase Request[5:0]
Manual VCO Band[5:0]
PLL Charge Pump Current[4:0]
N0[1:0]
VCO Control Voltage[3:0]
Bit 2
Power
down
clocks
Power
down
DACs
Enable
SED
compare
fail
SED
compare
fail
1
LVDS DCI
level low
Delay
bypass
FIFO soft
align ack
FIFO Phase Offset[2:0]
Sync Averaging[2:0]
Bit 1
Power
down
FIFO
Enable
FIFO
Warning 1
0
FIFO
Warning 1
1
LVDS data
level high
FIFO soft
align
request
Data Bus Width[1:0]
DCI Delay[1:0]
N1[1:0]
Bit 0
Power
down
filters
Enable
FIFO
Warning 2
0
FIFO
Warning 2
1
LVDS data
level low
Data Sheet
Default
0x00
0x10
0x00
0x00
0x00
0x00
N/A
N/A
0x3F
0x40
0xD1
0xD9
N/A
N/A
0x48
0x00
N/A
N/A
N/A
0x00
0x04
N/A
N/A