AD9125 Analog Devices, AD9125 Datasheet - Page 23

• Manufacturer Part Number: AD9125
• Manufacturer: Analog Devices

Specifications of AD9125

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

Register
Name
PLL Control 1
PLL Control 2
PLL Control 3
PLL Status 1
PLL Status 2
Sync Control 1
Address
(Hex)
0x0A
0x0C
0x0D
0x0E
0x0F
0x10
Bits
7
6
[5:0]
[7:5]
[4:0]
[7:6]
4
[3:2]
[1:0]
7
[3:0]
[5:0]
7
6
3
[2:0]
Name
PLL enable
PLL manual enable
Manual VCO band
PLL loop
bandwidth[2:0]
PLL charge pump
current[4:0]
N2[1:0]
PLL cross control enable
N0[1:0]
N1[1:0]
PLL lock
VCO control
voltage[3:0]
VCO band
readback[5:0]
Sync enable
Data/FIFO rate toggle
Rising edge sync
Sync averaging[2:0]
Rev. 0 | Page 23 of 56
Description
1 = enables the PLL clock multiplier. REFCLK input is
used as the PLL reference clock signal.
Enables the manual selection of the VCO band.
1 = manual mode; the correct VCO band must be
determined by the user.
Selects the VCO band to be used.
Selects the PLL loop filter bandwidth.
000 = loop bandwidth is nominally 200 kHz
010 = loop bandwidth is nominally 450 kHz
100 = loop bandwidth is nominally 950 kHz
110 = loop bandwidth is nominally 2 MHz
Sets the nominal PLL charge-pump current.
00000 = lowest current setting.
11111 = highest current setting.
PLL control clock divider. These bits determine the ratio
of the DACCLK rate to the PLL controller clock rate.
f
00 = f
01 = f
10 = f
11 = f
Enables PLL cross-point controller.
PLL VCO divider. These bits determine the ratio of the
VCO output to the DACCLK frequencies.
00 = f
01 = f
10 = f
11 = f
PLL loop divider. These bits determine the ratio of the
DACCLK to the REFCLK frequencies.
00 = f
01 = f
10 = f
11 = f
The PLL generated clock is tracking the REFCLK input
signal.
VCO control voltage readback (see Table 25).
Indicates the VCO band currently selected.
1 = enables the synchronization logic.
0 = operates the synchronization at the FIFO reset rate.
1 = operates the synchronization at the data rate.
0 = sync is initiated on the falling edge of the sync input.
1 = sync is initiated on the rising edge of the sync input.
Sets the number of input samples that are averaged for
determining the sync phase.
000 = 1.
001 = 2.
010 = 4.
011 = 8.
100 = 16.
101 = 32.
PC_CLK
DACCLK
DACCLK
DACCLK
DACCLK
VCO
VCO
VCO
VCO
DACCLK
DACCLK
DACCLK
DACCLK
must always be less than 80 MHz.
/f
/f
/f
/f
DACCLK
DACCLK
DACCLK
DACCLK
/f
/f
/f
/f
/f
/f
/f
/f
PC_CLK
PC_CLK
PC_CLK
PC_CLK
REFCLK
REFCLK
REFCLK
REFCLK
= 1.
= 2.
= 4.
= 4.
= 2.
= 4.
= 8.
= 16.
= 2.
= 4.
= 8.
= 16.
AD9125
Default
0
1
0
110
10001
3
1
10
01
R
R
R
0
1
1
0