AD9125 Analog Devices, AD9125 Datasheet - Page 40

• Manufacturer Part Number: AD9125
• Manufacturer: Analog Devices

Specifications of AD9125

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

AD9125
DAC INPUT CLOCK CONFIGURATIONS
DAC INPUT CLOCK CONFIGURATIONS
The AD9125 DAC sample clock (DACCLK) can be sourced
directly or by clock multiplying. Clock multiplying employs the
on-chip phased-locked loop (PLL) that accepts a reference clock
operating at a submultiple of the desired DACCLK rate, most
commonly the data input frequency. The PLL then multiplies
the reference clock up to the desired DACCLK frequency, which
can be used to generate all the internal clocks required by the
DAC. The clock multiplier provides a high quality clock that
meets the performance requirements of most applications. Using
the on-chip clock multiplier removes the burden of generating
and distributing the high speed DACCLK.
The second mode bypasses the clock multiplier circuitry and
allows DACCLK to be sourced directly to the DAC core. This
mode enables the user to source a very high quality clock directly
to the DAC core. Sourcing the DACCLK directly through the
REFCLKP, REFCLKN, DACCLKP, and DACCLKN pins may
be necessary in demanding applications that require the lowest
possible DAC output noise, particularly when directly synthesizing
signals above 150 MHz.
Driving the DACCLK and REFCLK Inputs
The REFCLK and DACCLK differential inputs share similar
clock receiver input circuitry. Figure 63 shows a simplified circuit
diagram of the input. The on-chip clock receiver has a differential
input impedance of about 10 kΩ. It is self-biased to a common-
mode voltage of about 1.25 V. The inputs can be driven by directly
coupling differential PECL or LVDS drivers. The inputs can also be
ac-coupled if the driving source cannot meet the input compliance
voltage of the receiver.
Figure 63. Clock Receiver Input Equivalent Circuit
DACCLKP,
REFCLKP
DACCLKN,
REFCLKN
5kΩ
5kΩ
REFCLKP/REFCLKN
(PIN 69 AND PIN 70)
1.25V
DACCLKP/DACCLKN
(PIN 2 AND PIN 3)
REGISTER 0x06, BITS[7:6]
REGISTER 0x0A, BIT 7
PLL LOCK LOST
PLL LOCKED
DETECTION
REGISTER 0x0D,
PHASE
Figure 64. PLL Clock Multiplication Circuit
PLL ENABLE
BITS[1:0]
÷N1
N1
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FILTER
PLL LOGIC CONTROL CLOCK
LOOP
REGISTER 0x0D,
BITS[3:2]
÷N2
The minimum input drive level to either clock input is
200 mV p-p differential. The optimal performance is achieved
when the clock input signal is between 800 mV p-p differential and
1.6 V p-p differential. Whether using the on-chip clock multiplier
or sourcing the DACCLK directly, it is necessary that the input
clock signal to the device has low jitter and fast edge rates to
optimize the DAC noise performance.
Direct Clocking
Direct clocking with a low noise clock produces the lowest noise
spectral density at the DAC outputs. To select the differential clock
inputs as the source for the DAC sampling clock, set the PLL
enable bit (Register 0x0A, Bit 7) to 0. This powers down the
internal PLL clock multiplier and selects the input from the
DACCLKP and DACCLKN pins as the source for the internal
DAC sample clock.
The device also has duty-cycle correction circuitry and differential
input-level correction circuitry. Enabling these circuits can provide
improved performance in some cases. The control bits for these
functions can be found in Register 0x08 (see Table 11).
Clock Multiplication
The on-chip PLL clock multiplier circuit can be used to generate
the DAC sample rate clock from a lower frequency reference
clock. When the PLL enable bit (Register 0x0A, Bit 7) is set to 1,
the clock multiplication circuit generates the DAC sample clock
from the lower rate REFCLK input. The functional diagram of
the clock multiplier is shown in Figure 64.
The clock multiplication circuit operates such that the VCO
outputs a frequency, f
frequency multiplied by N1 × N0.
The DAC sample clock frequency, f
The output frequency of the VCO must be chosen to keep f
in the optimal operating range of 1.0 GHz to 2.1 GHz. The
frequency of the reference clock and the values of N1 and N0
must be chosen so that the desired DACCLK frequency can be
synthesized and the VCO output frequency is in the correct range.
÷N0
N0
ADC
REGISTER 0x0D, BITS[7:6]
N2
f
f
VCO
VCO
DACCLK
= f
DACCLK
REFCLK
= f
REGISTER 0x0E, BITS[3:0]
VCO CONTROL
VOLTAGE
REFCLK
× (N1 × N0)
× N1
VCO
, equal to the REFCLK input signal
DACCLK
, is equal to
VCO