AD5722R Analog Devices, AD5722R Datasheet
AD5722R
Specifications of AD5722R
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AD5722R Summary of contents
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... The parts offer guaranteed monotonicity, integral nonlinearity (INL) of ±16 LSB maximum, low noise, 10 μs maximum settling time, and an on-chip +2.5 V reference. The AD5722R/AD5732R/AD5752R use a serial interface that operates at clock rates MHz and are compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs ...
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... Load DAC ( LDAC )..................................................................... 22 Asynchronous Clear ( CLR )....................................................... 22 Configuring the AD5722R/AD5732R/AD5752R .................. 22 REVISION HISTORY 7/11—Rev Rev. D Changes to Table 4: t7, t8, t10 Limits......................................................6 3/11—Rev Rev. C Changes to Configuring the AD5722R/AD5732R/ AD5752R Section ........................................................................... 22 8/10—Rev Rev. B Changes to Table 28........................................................................ 28 4/10—Rev Rev. A Changes to Junction Temperature, T max Parameter, Table Changes to Exposed Paddle Description, Table 6 ...
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... V 0.5 0.9 V ±4 ppm FSR/° kΩ 4000 pF 0.5 Ω Rev Page AD5722R/AD5732R/AD5752R = 2 5 kΩ; CC LOAD Test Conditions/Comments Outputs unloaded All models, guaranteed monotonic error at other temperatures A obtained using bipolar zero 25°C, error at other temperatures A obtained using zero-scale 25° ...
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... Power-Down Currents For specified performance, the headroom requirement is 0 INL is the relative accuracy measured from Code 512, Code 128, and Code 32 for the AD5752R, AD5732R, and AD5722R, respectively. 3 Guaranteed by characterization; not production tested. Min Typ Max Unit 2 V 0.8 V ± ...
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... Min Typ Max 10 12 7.5 8 320 Rev Page AD5722R/AD5732R/AD5752R = 2 5 LOAD Unit Test Conditions/Comments μ step to ±0.03% FSR μ step to ±0.03% FSR μs 512 LSB step settling (16-bit resolution) V/μs nV-sec mV nV-sec nV-sec nV-sec μV p-p 0x8000 DAC code μ ...
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... AD5722R/AD5732R/AD5752R TIMING CHARACTERISTICS −4 −16 200 pF; all specifications LOAD MIN Table Parameter Limit MIN MAX 100 130 ...
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... D0B D32B INPUT WORD FOR DAC N INPUT WORD FOR DAC N – DB23 UNDEFINED INPUT WORD FOR DAC N Figure 3. Daisy-Chain Timing Diagram Rev Page AD5722R/AD5732R/AD5752R D0B DB0 ...
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... AD5722R/AD5732R/AD5752R SCLK 1 SYNC DB23 SDIN INPUT WORD SPECIFIES REGISTER TO BE READ DB23 SDO DB0 DB23 DB0 DB23 UNDEFINED Figure 4. Readback Timing Diagram Rev Page DB0 NOP CONDITION DB0 SELECTED REGISTER DATA CLOCKED OUT ...
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... Exposure to absolute + 0 maximum rating conditions for extended periods may affect device reliability ESD CAUTION max − T )/θ Rev Page AD5722R/AD5732R/AD5752R ...
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... It is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance OUT OUT SIG_GND AD5722R/ SIG_GND BIN/2sCOMP 5 20 AD5732R/ NC DAC_GND 6 19 AD5752R SYNC 7 18 DAC_GND TOP VIEW (Not to Scale) REFIN/REFOUT SCLK 8 17 SDIN SDO 9 ...
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... AV /AV = +6.5V/0V, RANGE = + 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 500 1000 1500 2000 2500 CODE Figure 8. AD5722R Integral Nonlinearity Error vs. Code 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8 50,000 60,000 Figure 9. AD5752R Differential Nonlinearity Error vs. Code 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 Figure 10. AD5732R Differential Nonlinearity Error vs. Code ...
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... AD5722R/AD5732R/AD5752R –2 –4 –6 –8 –40 – TEMPERATURE (°C) Figure 12. AD5752R Integral Nonlinearity Error vs. Temperature 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –40 – TEMPERATURE (°C) Figure 13. AD5752R Differential Nonlinearity Error vs. Temperature –2 –4 –6 – ...
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... Figure 23. Digital Current vs. Logic Input Voltage Rev Page AD5722R/AD5732R/AD5752R ±5V RANGE ±10V RANGE – TEMPERATURE (°C) ±5V ±10V +10V – TEMPERATURE (°C) Figure 22 ...
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... AD5722R/AD5732R/AD5752R 0.010 ±5V RANGE, CODE = 0xFFFF ±10V RANGE, CODE = 0xFFFF +10V RANGE, CODE = 0xFFFF +5V RANGE, CODE = 0xFFFF 0.005 ±5V RANGE, CODE = 0x0000 ±10V RANGE, CODE = 0x0000 0 –0.005 –0.010 –0.015 –0.020 –25 –20 –15 –10 –5 0 OUTPUT CURRENT (mA) Figure 24 ...
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... LINE 73.8V CH1 1 CH1 LINE 73.8V Figure 34. REFOUT Output Noise (100 kHz Bandwidth) = ±16.5V 1 CH1 70 90 Figure 35. REFOUT Output Noise (0 Bandwidth) Rev Page AD5722R/AD5732R/AD5752R 5V CH2 500mV M 200µs CH1 2.9V Figure 33. REFOUT Turn-On Transient 100mV M 5s LINE 10mV M 5s LINE 1.2V 1.2V ...
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... /AV = ±6.5V, RANGE = ± /AV = +6.5V/0V, RANGE = + 500 1000 1500 2000 2500 3000 CODE Figure 39. AD5722R Total Unadjusted Error vs. Code 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 TEMPERATURE COEFFICIENT (ppm/°C) Figure 40. Reference Output TC (−40°C to +85° ...
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... TEMPERATURE (°C) Figure 42. Reference Output Voltage vs. Temperature (−40°C to+ 85°C) 2.50120 2.50100 2.50080 2.50060 2.50040 2.50020 2.50000 2.49980 Figure 43. Reference Output Voltage vs. Temperature (0°C to 85°C) Rev Page AD5722R/AD5732R/AD5752R 20 DEVICES SHOWN TEMPERATURE (°C) 80 ...
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... TUE is expressed in % FSR. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5722R/AD5732R/AD5752R power on normally specified as the area of the glitch in nV-sec (see Figure 32). Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state but the output voltage remains constant ...
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... LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec. AD5722R/AD5732R/AD5752R Voltage Reference TC Voltage reference measure of the change in the refer ence output voltage with a change in temperature. This value is expressed in ppm/° ...
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... V to ±16 addition, the parts have software-selectable output ranges +10 V, +10.8 V, ±5 V, ±10 V, and ±10.8 V. Data is written to the AD5722R/AD5732R/AD5752R in a 24-bit word format via a 3-wire serial interface. The devices also offer an SDO pin to facilitate daisy chaining or readback. ...
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... Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of AD5722R/AD5732R/AD5752R devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register ...
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... TRANSFER FUNCTION Table 8 to Table 16 show the relationships of the ideal input code to output voltage for the AD5752R, AD5732R, and AD5722R, respectively, for all output voltage ranges. For unipolar output ranges, the data coding is straight binary. For bipolar output ranges, the data coding is user selectable via the BIN/ 2sCOMP pin and can be either offset binary or twos complement ...
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... REFIN × (1/65,536) 0000 0000 0000 0000 0 V AD5722R/AD5732R/AD5752R Analog Output ±10 V Output Range +4 × REFIN × (32,767/32,768) +4 × REFIN × (32,766/32,768) … +4 × REFIN × (1/32,768 −4 × REFIN × (1/32,768) … ...
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... AD5722R/AD5732R/AD5752R Ideal Output Voltage to Input Code Relationship—AD5732R Table 11. Bipolar Output, Offset Binary Coding Digital Input MSB LSB 11 1111 1111 1111 11 1111 1111 1110 … … … … 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 … … … … ...
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... Ideal Output Voltage to Input Code Relationship—AD5722R Table 14. Bipolar Output, Offset Binary Coding Digital Input MSB LSB ±5 V Output Range 1111 1111 1111 +2 × REFIN × (2047/2048) 1111 1111 1110 +2 × REFIN × (2046/2048) … … … … 1000 0000 0001 +2 × ...
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... AD5722R/AD5732R/AD5752R INPUT SHIFT REGISTER The input shift register is 24 bits wide and consists of a read/write bit ( reserved bit (ZERO), which must always be set to 0; three register select bits (REG2, REG1, REG0); three DAC address bits (A2, A1, A0); and 16 data bits (data). The register data is clocked in MSB first on the SDIN pin ...
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... The DAC register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer is to take place (see Table 18). The data bits are in positions DB15 to DB0 for the AD5752R (see Table 19), DB15 to DB2 for the AD5732R (see Table 20), and DB15 to DB4 for the AD5722R (see Table 21). Table 19. Programming the AD5752R DAC Register ...
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... The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the power and thermal status of the AD5722R/AD5732R/AD5752R. The power control register options are shown in Table 27 and Table 28. Table 27. Programming the Power Control Register ...
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... G1 G2 Figure 48. Analog Output Control Circuitry POWER-DOWN MODE Each DAC channel of the AD5722R/AD5732R/AD5752R can be individually powered down. By default, all channels are in power-down mode. The power status is controlled by the power control register (see Table 27 and Table 28 for details). When a channel is in power-down mode, its output pin is clamped to ground through a resistance of approximately 4 kΩ ...
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... The printed circuit board on which the AD5722R/AD5732R/AD5752R are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5722R/ AD5732R/AD5752R are in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only ...
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... LSB −40°C to 85°C ±4 LSB −40°C to 85°C ±16 LSB −40°C to 85°C ±16 LSB Rev Page AD5722R/AD5732R/AD5752R 3.25 3.20 3.15 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. ...
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... AD5722R/AD5732R/AD5752R NOTES ©2008–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06466-0-7/11(D) Rev Page ...