AD5722R Analog Devices, AD5722R Datasheet - Page 22

• Manufacturer Part Number: AD5722R
• Description: Complete, Dual, 12-Bit, Serial Input, Unipolar/Bipolar, Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5722R

• Resolution (bits): 12bit
• Dac Update Rate: 1.07MSPS
• Dac Settling Time: 7.5µs
• Max Pos Supply (v): +16.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5722R/AD5732R/AD5752R
LOAD DAC (LDAC)
After data has been transferred into the input register of the
DACs, there are two ways to update the DAC registers and DAC
outputs. Depending on the status of both SYNC and LDAC , one
of two update modes is selected: individual DAC updating or
simultaneous updating of all DACs.
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the input shift register. The addressed DAC output is updated
on the rising edge of SYNC .
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the input shift register. All DAC outputs are asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC .
ASYNCHRONOUS CLEAR (CLR)
CLR is an active low clear that allows the outputs to be cleared
to either zero-scale code or midscale code. The clear code value
is user selectable via the CLR select bit of the control register
(see the
CLR low for a minimum amount of time to complete the operation
(see
remains at the cleared value until a new value is programmed. The
outputs cannot be updated with a new value while the CLR pin
is low. A clear operation can also be performed via the clear
command in the control register.
Figure 47. Simplified Diagram of Input Loading Circuitry for One DAC
Figure 2
Control Register
REFIN
LDAC
SYNC
SCLK
SDIN
). When the
12-/14-/16-BIT
INTERFACE
REGISTER
REGISTER
CLR signal is returned high, the output
section). It is necessary to maintain
INPUT
LOGIC
DAC
DAC
AMPLIFIER
OUTPUT
SDO
V
OUT
x
Rev. D | Page 22 of 32
CONFIGURING THE AD5722R/AD5732R/AD5752R
When the power supplies are applied to the AD5722R/AD5732R/
AD5752R, the power-on reset circuit ensures that all registers
default to 0. This places all channels and the internal reference
in power-down mode. The DV
any of the interface lines are powered. If this is not done the first
write to the device may be ignored. The first communication to
the AD5722R/AD5732R/AD5752R should be to set the required
output range on all channels (the default range is the 5 V unipolar
range) by writing to the output range select register. The user
should then write to the power control register to power on the
required channels and the internal reference, if required.
If an external reference source is being used, the internal
reference must remain in power-down mode. To program an
output value on a channel, that channel must first be powered
up; any writes to a channel while it is in power-down mode are
ignored. The AD5722R/AD5732R/AD5752R operate with a
wide power supply range. It is important that the power supply
applied to the parts provides adequate headroom to support the
chosen output ranges.
TRANSFER FUNCTION
Table 8 to Table 16 show the relationships of the ideal input code
to output voltage for the AD5752R, AD5732R, and AD5722R,
respectively, for all output voltage ranges. For unipolar output
ranges, the data coding is straight binary. For bipolar output
ranges, the data coding is user selectable via the BIN/ 2sCOMP
pin and can be either offset binary or twos complement.
For a unipolar output range, the output voltage expression is
given by
For a bipolar output range, the output voltage expression is given by
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
V
Gain is an internal gain whose value depends on the output
range selected by the user, as shown in Table 7.
Table 7.
Output Range (V)
+5
+10
+10.8
±5
±10
±10.8
REFIN
V
V
is the reference voltage applied at the REFIN pin.
OUT
OUT
=
=
V
V
REFIN
REFIN
×
×
Gain
Gain
⎡
⎢ ⎣
⎡
⎢ ⎣
2
2
D
D
N
N
CC
⎤
⎥ ⎦
⎤
⎥ ⎦
should be brought high before
−
Gain
×
Gain Value
2
4
4.32
4
8
8.64
2
V
REFIN