CS181012-CQZ Cirrus Logic Inc, CS181012-CQZ Datasheet - Page 23

• Manufacturer Part Number: CS181012-CQZ
• Description: IC COBRANET CS181012 144LQFP
• Manufacturer: Cirrus Logic Inc
• Series: CobraNet®r
• Type: Audio Processorr

Specifications of CS181012-CQZ

• Package / Case: 144-LQFP
• Applications: Data Transport
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Number Of Converters: 8
• Core Size: 32 Bit
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Supply Voltage Min: 3.13V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1021 - MODULE COBRANET 4961 CM2 FB598-1020 - MODULE COBRANET 1810 CM2 MT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1025

7.0 Host Management Interface (HMI)
7.1
DS651UM23
Version 2.3
Hardware
The host port is 8 bits wide with 4 bits of addressing. Ten of the 16 addressable registers
are implemented. The upper two registers can be used to configure and retrieve the
status on the host port hardware. However, only the first 8 are essential for normal HMI
communications. It is therefore feasible, in most applications, to utilize only the first 3
address bits and tie the most significant bit (A3) low.
Host port hardware supports Intel
bus (big-endian) protocols. Standard CobraNet firmware configures the port in the
Motorola, big-endian mode.
The host port memory map is shown in
page 33
The message and data registers provide separate bi-directional data conduits between
the host processor and the CS1810xx/CS4961xx. A 32-bit word of data is transferred to
the CS1810xx/CS4961xx when the host writes the D message or data register after
presumably previously writing the A, B, and C registers with valid data. Data is transferred
from the CS1810xx/CS4961xx following a read of the D message or data register. Again,
presumably the A, B, and C registers are read previously.
Two additional hardware signals are associated with the host port: HACK and HREQ.
Both are outputs to the host.
HACK may be wired to an interrupt request input on the host. HACK can be made to
assert (logic 0) on specific events as specified by the hackEnable MI variable. HACK is
deasserted (logic 1) by issuance of the Acknowledge Interrupt message (see “Messages”
below).
0
1
2
3
4
5
6
7
8
9
and
Host Address
"HMI Access Code" on page
Table 3. Host port memory map
©
Copyright 2005 Cirrus Logic, Inc.
Message A (MS)
Message B
Message C
Message D (LS)
Data A (MS)
Data B
Data C
Data D (LS)
Control
Status
®
(little-endian), Motorola
Table
34.
Register
3. Refer also to
®
CobraNet Hardware User’s Manual
Host Management Interface (HMI)
, and Motorola multiplexed
"HMI Definitions" on
23