CS181012-CQZ Cirrus Logic Inc, CS181012-CQZ Datasheet - Page 32

• Manufacturer Part Number: CS181012-CQZ
• Description: IC COBRANET CS181012 144LQFP
• Manufacturer: Cirrus Logic Inc
• Series: CobraNet®r
• Type: Audio Processorr

Specifications of CS181012-CQZ

• Package / Case: 144-LQFP
• Applications: Data Transport
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Number Of Converters: 8
• Core Size: 32 Bit
• Digital Ic Case Style: LQFP
• No. Of Pins: 144
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: 0°C To +70°C
• Filter Terminals: SMD
• Supply Voltage Min: 3.13V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1021 - MODULE COBRANET 4961 CM2 FB598-1020 - MODULE COBRANET 1810 CM2 MT
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1025

CobraNet Hardware User’s Manual
Host Management Interface (HMI)
7.4.3 Data
32
Before accessing data, address setup must be performed. Address setup consists of
issuing a Translate Address request, waiting for the request to complete, then issuing a
Goto Translation.
Pipelining requires that a “garbage read” be performed following an address change. The
second word read contains the data for the address requested. No similar pipelining issue
exists with respect to write operations.
7.4.3.1. Region length
Distance from the original pointer position (as per Translate Address) to the end of the
instantiated region. A value of 0 indicates an invalid pointer.
7.4.3.2. Writable Region
When set, this bit indicates the address pointer is positioned within a writable region. MI
variables may be modified in a writable region by writing data to the data conduit.
7.4.3.3. Translation Complete
When set, this bit indicates that the address translator is available (translation results are
available and a new translation request may be submitted). This bit is cleared when a
Translate Address message is issued and is set when the translation completes.
7.4.3.4. Packet Transmission Complete
This bit is cleared when transmission is initiated by issuance of the Transmit Packet
message. The bit is set when the packet has been transmitted and the transmit buffer is
ready to accept a new packet.
7.4.3.5. Received Packet Available
This bit is set when a packet is received into the packet bridge. It is cleared when the
packet data is read and receipt is acknowledged by issuance of an Acknowledge Packet
Receipt message. Note that Received Packet Available only goes low when there are no
longer any pending received packets for the packet bridge. The packet bridge has the
capacity to queue multiple packets in the receive direction.
7.4.3.6. Message Togglebit
This bit toggles on completion of processing of each message. A safe means for the host
to acknowledge processing of messages is as follows:
void WaitToggle( void )
{
}
int msgack = MSG_D; /* clean pipeline */
msgack = MSG_D; /* record current state of togglebit */
MSG_D = YOUR_COMMAND_HERE; /* issue command */
/* wait for togglebit to flip */
while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) );
©
Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3