AD5644R Analog Devices, AD5644R Datasheet - Page 24

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AD5644R

Manufacturer Part Number
AD5644R
Description
Manufacturer
Analog Devices
Datasheet

Specifications of AD5644R

Resolution (bits)
14bit
Dac Update Rate
250kSPS
Dac Settling Time
3.5µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD5644RBRMZ-5
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD5624R/AD5644R/AD5664R
MICROPROCESSO
AD5624R/AD5644R/AD5664R to Blackfin ADSP-BF
Interface
Figure 57 shows a serial interface between the AD5624R/
AD5644R/AD5664R and the Blackfin® ADSP-BF53x micro-
processor. The ADSP-BF53x processor family incorporates tw
dual-channel synchronous serial ports, SPORT1 and SPORT0,
for serial and multiproc
to connect to the AD5624R/AD5644R/AD5664R, the setup
the interface is that the DT0PRI drives the DIN pin of the
AD5624R/AD5644R/AD5664R, while TSCLK0 drives the
SCLK of the part. The SYNC is driven from TFS0.
AD5624R/AD5644R/AD5664R to 68HC11/68L11
Interface
Figure 58 shows a serial interface between the AD5624R/
AD5644R/AD5664R and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5624R/
AD5644R/AD5664R, while the MOSI output drives the serial
data line of the DAC.
The SYNC signal is derived from a port line (PC7). The setup
c
68H
CPHA bit as 1. When data is transmitted to the DAC, the SYNC
line is taken low
as descri
va
68L11 is tra
edges occurring in the tran
first. To load data to the AD5624R/AD5644R/AD5664R, PC7 is
left low after the first eight bits are transferred, and a second
serial write oper
high at t
onditions for correct operation of this interface are that the
Figure 57. Blackfin ADSP-BF53x Interface to AD5624R/AD5644R/AD566
lid on the falling
Figure 58. 68HC11/68L11 Interface to AD5624R/AD5644R/AD5664R
C11/68L11 is configured with its CPOL bit as 0 and its
he end of thi
bed previo
nsmitted in 8
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
68HC11/68L11
ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-BF53x
ation is performed to the DAC; PC7 is taken
(PC7). When the 68HC11/68L11 is configured
TSCLK0
DTOPRI
usly, da appear g on the
ed
TFS0
s proced
MOSI
ge of S
SCK
PC7
R INTERFACING
essor communications. Using SPORT0
1
-bit bytes with o
1
ta
smit cycle. Da
CK
ure
. Seria
.
in
SYNC
DIN
SCLK
AD5664R
AD5624R/
AD5644R/
SYNC
SCLK
DIN
l da
AD5664R
AD5624R/
AD5644R/
nly eight fallin
ta is tran
ta from he 68H
M
1
1
OSI o
t
smitted MSB
utp
g clock
53x
C1
ut is
for
1/
Rev. B | Page 24 of 28
4R
o
AD5624R/AD5644R/AD5664R to 80C51/80L51 Interface
Figure 59 shows a serial interface between the AD5624R/
AD5644R/AD5664R and the 80C51
setup for the interface is that the TxD of the 80C51
SCLK of the
serial data line o
prog
When data is transmitted
P3
only; thus, only eight fall
To load data to the DAC,
transmitted, and a second write cycle is in
second byte of data. P3.3 is taken high foll
this cycle. The 80C51/80L51 outputs the serial data in LSB first
format. The AD5624R/AD5644R/AD5664R must receive data with
the MSB first. The 80C51/80L51 transmit routine should take this
into account.
AD
Fi
A
is shifted out on the falling edge of the serial clock and is
clocked into the AD5624R/AD5644R/AD5664R on the rising
edge of the SK.
D5664R and any MICROWIRE-compatible device. Serial data
gure 60 shows an inter
.3 is taken low. The 80
5624R/AD5644R/
rammable pin on th
Fig
Figure 60. MICROWIRE Interface to AD5624R/AD5644R/AD5664R
ure 59. 80C51/80L5
1
1
AD5624R/AD5644R/AD5664R, while R
ADDITIONAL
ADDITIONAL PINS OMITTED FOR CLARITY.
80C51/80L51
MICROWIRE
f the par
P3.3
RxD
TxD
PINS OMITTED FOR CLARITY.
SO
AD5664R to MICROW
CS
SK
t. The SYNC signal is derived from a bit-
C51/80L51 transmits data in 8-bit bytes
ing clock edges occur in the transmit cycle.
1 Interface
e port. In this case, port line P3.3 is used.
P3.3 is left low aft
face between t
1
to the AD5624R/AD5644R/AD5664R,
1
to AD5624R/AD5644R/AD5664R
/80L51 microcontroller. The
SYNC
SCLK
DIN
SYNC
SCLK
DIN
AD5664R
AD5
AD5624R/
AD5644R/
AD5624R/
AD5
he AD5624R/AD5644R/
itiated to transmit the
owing the completion of
er the first eight bits are
664R
644R
1
1
IRE Interface
/
/80L51 drives
xD drives the

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