AD5644R Analog Devices, AD5644R Datasheet - Page 9

• Manufacturer Part Number: AD5644R
• Manufacturer: Analog Devices

Specifications of AD5644R

• Resolution (bits): 14bit
• Dac Update Rate: 250kSPS
• Dac Settling Time: 3.5µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
V
V
GND
V
V
SYNC
SCLK
DIN
V
V
OUT
OUT
OUT
OUT
DD
REFIN
A
B
C
D
/V
REFOUT
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for all Circuitry on the Part.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling
edges of the next 24 clocks. If SYNC is taken high before the 24
interrupt and the write sequence is ignored by the device.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 50 MHz.
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
The AD5624R/AD5644R/AD5664R have a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is the reference input
pin. The default for this pin is as a reference input.
V
V
V
V
OUT
OUT
OUT
OUT
GND
A
B
C
D
GND ON LFCSP PACKAGE
EXPOSED PAD TIED TO
1
2
3
4
5
Figure 3. Pin Configuration
(Not to Scale)
AD5624R/
AD5644R/
AD5664R
TOP VIEW
Rev. B | Page 9 of 28
10
9
8
7
6
V
V
DIN
SCLK
SYNC
REFIN
DD
/V
REFOUT
th
falling edge, the rising edge of SYNC acts as an
AD5624R/AD5644R/AD5664R