AD5764 Analog Devices, AD5764 Datasheet
AD5764
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AD5764 Summary of contents
Page 1
... During power-up (when the supply voltages are changing), VOUTx is clamped via a low impedance path. The AD5764 uses a serial interface that operates at clock rates MHz and is compatible with DSP and microcontroller interface standards. Double buffering allows the simultaneous updating of all DACs ...
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... Characteristics Section .................................................................. 13 Changes to Table 16 ....................................................................... 22 Changes to Table 18 ....................................................................... 23 Changes to Typical Operating Circuit Section........................... 28 Changes to AD5764 to ADSP-2101 Section ............................... 29 Changes to Ordering Guide .......................................................... 30 1/07—Rev Rev. A Changes to Absolute Maximum Ratings..................................... 10 Changes to Figure 25 and Figure 26............................................. 16 3/06—Revision 0: Initial Version Rev Page Data Sheet ...
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... DATA REG D REG D GAIN REG D OFFSET REG D REFERENCE LDAC Figure 1. Rev Page RSTOUT RSTIN REFAB VOLTAGE MONITOR AND CONTROL BUFFERS G1 DAC DAC DAC DAC D G2 BUFFERS REFCD AD5764 ISCC VOUTA AGNDA VOUTB AGNDB VOUTC AGNDC VOUTD AGNDD ...
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... AD5764 SPECIFICATIONS −11 −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 2 5. kΩ LOAD guaranteed to +105°C with degraded performance. All specifications T Table 2. Parameter ACCURACY Resolution Relative Accuracy (INL) Differential Nonlinearity Bipolar Zero Error ...
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... LSB step settling V/μs typ nV-sec typ mV max dB typ nV-sec typ nV-sec typ nV-sec typ Effect of input bus activity on DAC outputs LSB p-p typ μV rms max kHz typ nV/√Hz typ Measured at 10 kHz nV/√Hz typ Measured at 10 kHz AD5764 ...
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... AD5764 TIMING CHARACTERISTICS −11 −16.5 V, AGNDx = DGND = REFGND = PGND = 0 V; REFAB = REFCD = 2 5. kΩ LOAD Table Parameter Limit ...
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... DB0 DB23 INPUT WORD FOR DAC N INPUT WORD FOR DAC N– DB23 UNDEFINED INPUT WORD FOR DAC N Figure 3. Daisy-Chain Timing Diagram Rev Page DB0 DB0 AD5764 ...
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... AD5764 SCLK SYNC DB23 SDIN SDO 24 DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ DB23 UNDEFINED Figure 4. Readback Timing Diagram 200µ SDO OH PIN 50pF 200µ Figure 5. Load Circuit for SDO Timing Diagram Rev Page ...
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... −0 0 (whichever is less) ESD CAUTION −0 0 −0 0 −0 +0.3 V −40°C to +85°C −65°C to +150°C 150°C 65°C/W 12°C/W JEDEC industry standard J-STD-020 Rev Page AD5764 ...
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... V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load. 20 AGNDC Ground Reference Pin for DAC C Output Amplifier AGNDA SYNC 1 24 PIN 1 VOUTA SCLK 2 23 VOUTB SDIN 3 22 AD5764 SDO AGNDB 4 21 TOP VIEW (Not to Scale) AGNDC CLR 5 20 VOUTC LDAC 6 19 VOUTD 7 18 ...
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... Reference Generator and Buffers. , input coding is offset binary. When hardwired to DGND, input coding is twos complement CC Rev Page ale output range of ± for specified performance. t range for specified performance DGND. When hardwired to CC AD5764 ...
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... AD5764 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 10000 20000 30000 40000 DAC CODE Figure 7. Integral Nonlinearity Error vs. Code, AV /AV = ± 1 25° /AV = ±12V 0 REFIN 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 10000 20000 30000 40000 DAC CODE Figure 8 ...
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... Figure 18. Differential Nonlinearity Error vs. Reference Voltage, Rev Page 11.4 12.4 13.4 14.4 15.4 SUPPLY VOLTAGE ( 25° /AV = ±16. REFERENCE VOLTAGE (V) AV /AV = ±16 25° / REFERENCE VOLTAGE (V) AV /AV = ±16 AD5764 T = 25° REFIN 16 ±16. ...
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... AD5764 0 25°C A 0.4 AV /AV = ±16. 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 –1 REFERENCE VOLTAGE (V) Figure 19. Total Unadjusted Error vs. Reference Voltage, AV /AV = ±16 25° REFIN 11.4 12.4 13.4 14.4 AV /AV ( Figure 20 ...
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... CH1 3.00V M1.00µs CH1 Figure 27. Full-Scale Settling Time –4 –6 –8 –10 –12 –14 –16 –18 – –22 REFIN T A 0x8000 TO 0x7FFF –24 500ns/DIV –26 –2.0–1.5–1.0–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 TIME (µs) AD5764 –120mV /AV = ±12V 25°C /AV = ± ...
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... AD5764 AV /AV = ±15V DD SS MIDSCALE LOADED REFIN 4 CH4 50.0µV M1.00s Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth REFIN 25° RAMP TIME = 100µs LOAD = 200pF||10kΩ CH1 10.0V CH2 10.0V M100µs A CH1 W B CH3 10.0mV T 29 ...
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... DNL vs. code plot can be seen in Figure 9. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5764 is monotonic over its full operating temperature range. Bipolar Zero Error Bipolar zero error is the deviation of the analog output from the ...
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... DAC and operates from supply voltages of ±11 ±16.5 V and has a buffered output voltage ±10.5263 V. Data is written to the AD5764 in a 24-bit word format, via a 3-wire serial interface. The device also offers an SDO pin that is available for daisy- chaining or readback. ...
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... Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD5764 devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register ...
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... Data Data bits. The output voltage expression for the AD5764 is given by where the decimal equivalent of the code loaded to the DAC. V REFIN ASYNCHRONOUS CLEAR (CLR) × (32,767/32,768) REF CLR is a negative edge triggered clear that allows the outputs to × ...
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... Clear, data = don’t care Load, data = don’t care DAC address DAC address CG1 Rev Page AD5764 DB3 DB2 DB1 D1 value D0 direction D0 value DB15:DB0 16-bit DAC data DB15: DB2 DB1 Don’t care CG1 CG0 0 1 ...
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... The offset register is addressed by setting the three REG bits to 101. The DAC address bits select with which DAC channel the data transfer is to take place (see Table 10). The AD5764 offset register is an 8-bit register and allows the user to adjust the offset of each channel by − ...
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... V introduces a gain error. An output range of ±10 V and twos complement data coding is assumed. Removing Offset Error The AD5764 can eliminate an offset error in the range of −4. +4.84 mV with a step size of ⅛ 16-bit LSB. Calculate the step size of the offset adjustment. 20 ...
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... DIGITAL I/O PORT The AD5764 contains a 2-bit digital I/O port (D1 and D0). These bits can be configured as inputs or outputs independently, and can be driven or have their values read back via the serial interface ...
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... Data Sheet APPLICATIONS INFORMATION TYPICAL OPERATING CIRCUIT Figure 36 shows the typical operating circuit for the AD5764. The only external components needed for this precision 16-bit DAC are a reference voltage source, decoupling capacitors on the supply pins and reference inputs, and an optional short- circuit current setting resistor ...
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... Choosing a reference with an output trim adjustment, such as the ADR425, allows a system designer to trim system errors out by setting the reference Table 20. Some Precision References Recommended for Use with the AD5764 Part No. Initial Accuracy (mV Max) ADR435 ± ...
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... The PCB on which the AD5764 is mounted must be designed so that the analog and digital sections are sepa- rated and confined to certain areas of the board. If the AD5764 system where multiple devices require an AGND-to-DGND connection, the connection made at one point only. The star ground point is established as close as possible to the device. The AD5764 must have ample supply bypassing of 10 μ ...
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... AD5764ASUZ ±4 LSB max AD5764ASUZ-REEL7 ±4 LSB max AD5764BSUZ ±2 LSB max AD5764BSUZ-REEL7 ±2 LSB max AD5764CSUZ ±1 LSB max AD5764CSUZ-REEL7 ±1 LSB max EVAL-AD5764EBZ RoHS Compliant Part. ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...