AD5764 Analog Devices, AD5764 Datasheet - Page 19

• Manufacturer Part Number: AD5764
• Description: Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC
• Manufacturer: Analog Devices

Specifications of AD5764

• Resolution (bits): 16bit
• Dac Update Rate: 1.26MSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Data Sheet
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines. The first falling edge of SYNC
starts the write cycle. The SCLK is continuously applied to the
input shift register when SYNC is low. If more than 24 clock
pulses are applied, the data ripples out of the input shift register
and appears on the SDO line. This data is clocked out on the
rising edge of SCLK and is valid on the falling edge. By connect-
ing the SDO of the first device to the SDIN input of the next device
in the chain, a multidevice interface is constructed. Each device in
the system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24N, where N is the total number of
AD5764 devices in the chain. When the serial transfer to all
devices is complete, SYNC is taken high. This latches the input
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift register. The serial
clock can be a continuous or a gated clock.
A continuous SCLK source can only be used if SYNC is held low
for the correct number of clock cycles. In gated clock mode, a burst
clock containing the exact number of clock cycles must be used,
and SYNC must be taken high after the final clock to latch the data.
Readback Operation
Before a readback operation is initiated, the SDO pin must be
enabled by writing to the function register and clearing the SDO
68HC11
MISO
1
Figure 33. Daisy-Chaining the AD5764
ADDITIONAL PINS OMITTED FOR CLARITY
MOSI
1
SCK
PC7
PC6
SDIN
SCLK
SYNC
LDAC
SCLK
SYNC
LDAC
SCLK
SYNC
LDAC
AD5764
AD5764
AD5764
SDIN
SDIN
SDO
SDO
SDO
1
1
1
Rev. F | Page 19 of 28
disable bit; this bit is cleared by default. Readback mode is invoked
by setting the R/ W bit = 1 in the serial input shift register write.
With R/ W = 1, Bit A2 to Bit A0, in association with Bit REG2,
Bit REG1, and Bit REG0, select the register to be read. The
remaining data bits in the write sequence are don’t cares. During
the next SPI write, the data appearing on the SDO output
contain the data from the previously addressed register. For a
read of a single register, the NOP command can be used in
clocking out the data from the selected register on SDO. The
readback diagram in
example, to read back the fine gain register of Channel A on the
AD5764, implement the following:
1.
2.
SIMULTANEOUS UPDATING VIA LDAC
Depending on the status of both SYNC and LDAC , and after
data has been transferred into the input register of the DACs,
there are two ways in which the data register and DAC outputs
can be updated.
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the input shift register. The addressed DAC output is updated
on the rising edge of SYNC .
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the input shift register. All DAC outputs are updated by
taking LDAC low any time after SYNC has been taken high.
The update now occurs on the falling edge of LDAC .
Write 0xA0XXXX to the AD5764 input shift register. This
configures the AD5764 for read mode with the fine gain
register of Channel A selected. Note that all the data bits,
DB15 to DB0, are don’t cares.
Follow this with a second write, an NOP condition,
0x00XXXX. During this write, the data from the fine gain
register is clocked out on the SDO line, that is, data clocked
out contain the data from the fine gain register in Bit DB5
to Bit DB0.
Figure 34. Simplified Serial Interface of Input Loading Circuitry
V
REFIN
LDAC
SYNC
SCLK
SDIN
Figure 4
for One DAC Channel
INTERFACE
REGISTER
REGISTER
16-BIT
DAC
INPUT
DATA
LOGIC
shows the readback sequence. For
I/V AMPLIFIER
OUTPUT
SDO
V
OUTx
AD5764