AD5628 Analog Devices, AD5628 Datasheet - Page 9

• Manufacturer Part Number: AD5628
• Manufacturer: Analog Devices

Specifications of AD5628

• Resolution (bits): 12bit
• Dac Update Rate: 95kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
14-Lead
TSSOP
N/A
1
2
3
11
4
10
7
N/A
5
9
6
8
12
13
14
V
REFIN
/V
Figure 3. 14-Lead TSSOP (RU-14)
REFOUT
V
V
V
V
SYNC
OUT
OUT
OUT
OUT
V
DD
G
A
C
E
16-Lead
TSSOP
1
2
3
4
13
5
12
8
9
6
11
7
10
14
15
16
Pin No.
1
2
3
4
5
6
7
(Not to Scale)
AD5628/
AD5648/
TOP VIEW
16-Lead
LFCSP
15
16
1
2
11
3
10
6
7
4
9
5
8
12
13
14
EPAD
14
13
12
11
10
9
8
SCLK
DIN
GND
V
V
V
V
OUT
OUT
OUT
OUT
B
D
F
H
Mnemonic
LDAC
SYNC
V
V
V
V
V
V
V
CLR
V
V
V
V
GND
DIN
SCLK
EPAD
DD
OUT
OUT
OUT
OUT
REFIN
REFOUT
OUT
OUT
OUT
OUT
A
B
C
D
E
F
G
H
/
V
REFIN
Description
Pulsing this pin low allows any or all DAC registers to be updated if the input registers
have new data. This allows all DAC outputs to simultaneously update. Alternatively, this
pin can be tied permanently low.
Active Low Control Input. This is the frame synchronization signal for the input data.
When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift
register. Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken
high before the 32
write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply
should be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
The AD5628/AD5648/AD5668 have a common pin for reference input and reference
output. When using the internal reference, this is the reference output pin. When using
an external reference, this is the reference input pin. The default for this pin is as a
reference input.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all
LDAC pulses are ignored. When CLR is activated, the input register and the DAC register
are updated with the data contained in the CLR code register—zero, midscale, or full
scale. Default setting clears the output to 0 V.
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register
on the falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the
serial clock input. Data can be transferred at rates of up to 50 MHz.
It is recommended that the exposed paddle be soldered to the ground plane.
/V
Figure 4. 16-Lead TSSOP (RU-16)
REFOUT
V
V
V
V
LDAC
SYNC
OUT
OUT
OUT
OUT
V
DD
G
A
C
E
Rev. F | Page 9 of 32
1
2
3
4
5
6
7
8
(Not to Scale)
AD5628/
AD5648/
AD5668
TOP VIEW
nd
falling edge, the rising edge of SYNC acts as an interrupt and the
15
14
13
12
11
10
16
9
SCLK
DIN
GND
V
V
V
V
CLR
OUT
OUT
OUT
OUT
B
D
F
H
AD5628/AD5648/AD5668
NOTES
1. EXPOSED PAD MUST BE TIED TO GND.
V
V
V
OUT
OUT
OUT
V
DD
Figure 5. 16-Lead LFCSP(CP-16-17)
A
C
E
1
4
2
3
AD5628/AD5668
(Not to Scale)
TOP VIEW
12
11
10
9
V
GND
V
V
OUT
OUT
OUT
B
D
F