AD5601 Analog Devices, AD5601 Datasheet - Page 4

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AD5601

Manufacturer Part Number
AD5601
Description
2.7 V to 5.5 V,
Manufacturer
Analog Devices
Datasheet

Specifications of AD5601

Resolution (bits)
8bit
Dac Update Rate
1.7MSPS
Dac Settling Time
6µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
Ser,SPI

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AD5601/AD5611/AD5621
Parameter
POWER REQUIREMENTS
POWER EFFICIENCY
1
2
3
TIMING CHARACTERISTICS
V
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
1
2
1
2
3
4
5
6
7
8
9
Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252.
Guaranteed by design and characterization, not production tested.
Total current flowing into all pins.
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
Maximum SCLK frequency is 30 MHz.
2
DD
V
I
I
I
DD
DD
OUT
DD
= 2.7 V to 5.5 V; all specifications T
V
V
V
V
for Normal Mode
/I
for All Power-Down Modes
DD
DD
DD
DD
DD
= ±4.5 V to ±5.5 V
= ±2.7 V to ±3.6 V
= ±4.5 V to ±5.5 V
= ±2.7 V to ±3.6 V
SCLK
SYNC
SDIN
Limit
33
5
5
10
5
4.5
0
20
13
1
t
8
t
4
Min
2.7
D15
MIN
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
to T
Typ
75
60
0.5
0.2
96
A Grade
D14
MAX
t
3
, unless otherwise noted. See Figure 2.
t
2
Max
5.5
100
90
DD
) and timed from a voltage level of (V
Figure 2. Timing Diagram
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK falling edge ignored
t
1
Rev. F | Page 4 of 24
D2
Min
2.7
t
Typ
75
60
0.5
0.2
96
5
B Grade
D1
t
6
D0
Max
5.5
100
90
t
7
IL
t
9
+ V
IH
Unit
V
µA
µA
µA
µA
%
)/2.
Test Conditions/Comments
All digital inputs at 0 V or V
DAC active and excluding load
current
V
V
V
V
V
I
LOAD
D15
IH
IH
IH
IH
IH
= V
= V
= V
= V
= V
= 2 mA and V
DD
DD
DD
DD
DD
and V
and V
and V
and V
and V
D14
IL
IL
IL
IL
IL
Data Sheet
= GND
= GND
= GND
= GND
= GND
DD
= ±5 V
DD

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