AD5425 Analog Devices, AD5425 Datasheet - Page 15

• Manufacturer Part Number: AD5425
• Description: High Bandwidth, CMOS 8-Bit Serial Interface Multiplying D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5425

• Resolution (bits): 8bit
• Dac Update Rate: 2.47MSPS
• Dac Settling Time: 100ns
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Ser,SPI

Bipolar Operation
In some applications, it may be necessary to generate full 4-
quadrant multiplying operation or a bipolar output swing. This
can be easily accomplished by using another external amplifier
and some external resistors, as shown in Figure 31. In this
circuit, the second amplifier, A2, provides a gain of 2. Biasing
the external amplifier with an offset from the reference voltage,
results in full 4-quadrant multiplying operation. The transfer
function of this circuit shows that both negative and positive
output voltages are created as the input data, D, is incremented
from code zero (V
scale (V
Where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.
When V
multiplication.
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation.
Table 6. Bipolar Code Table
Digital Input
1111 1111
1000 0000
0000 0001
0000 0000
V
OUT
OUT
IN
is an ac signal, the circuit performs 4-quadrant
=
= +V
(
V
REF
REF
OUT
×
).
= −V
D
2 /
n
REF
− 1
Analog Output (V)
+V
0
−V
−V
)
) to midscale (V
V
−
±10V
REF
REF
REF
REF
V
REF
(127/128)
(127/128)
(128/128)
NOTES:
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH
V
SPEED AMPLIFIER.
OUT
R1
= 0 V WITH CODE 10000000 LOADED TO DAC.
MICROCONTROLLER
SYNC
V
Figure 31. Bipolar Operation (4-Quadrant Multiplication)
REF
OUT
SCLK SDIN GND
= 0 V ) to full
AD5425
V
V
DD
DD
R
Rev. A | Page 15 of 28
FB
20kΩ
I
I
OUT
OUT
R3
1
2
R2
C1
AGND
Stability
In the I-to-V configuration, the I
inverting node of the op amp must be connected as closely as
possible and proper PCB layout techniques must be employed.
Since every code change corresponds to a step function, gain
peaking can occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in closed-loop
applications.
An optional compensation capacitor, C1, can be added in
parallel with R
31. Too small a value of C1 can produce ringing at
the output, while too large a value can adversely affect the
settling time. C1 should be found empirically, but 1 pF to
2 pF is generally adequate for compensation.
A1
A1
10kΩ
R4
FB
for stability, as shown in Figure 30 and Figure
20kΩ
A2
R5
V
TO +V
OUT
= –V
REF
REF
OUT
of the DAC and the
AD5425