AD5348 Analog Devices, AD5348 Datasheet - Page 17

• Manufacturer Part Number: AD5348
• Description: 2.5 V to 5.5 V, Parallel Interface Octal Voltage Output 12-Bit D/A Converter
• Manufacturer: Analog Devices

Specifications of AD5348

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par

PARALLEL INTERFACE
The AD5346/AD5347/AD5348 load their data as a single 8-,
10-, or 12-bit word.
Double-Buffered Interface
The AD5346/AD5347/AD5348 DACs all have double-buffered
interfaces consisting of an input register and a DAC register.
DAC data, BUF, and GAIN inputs are written to the input regis-
ter under control of the Chip Select ( CS ) and Write ( WR ) pins.
Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it. The gain and buffer control signals
are also double-buffered and are updated only when LDAC is
taken low.
This is useful if the user requires simultaneous updating of all
DACs and peripherals. The user can write to all input registers
individually and then, by pulsing the LDAC input low, all
outputs update simultaneously.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the input registers. In the case of the AD5346/
AD5347/AD5348, the part updates the DAC register only if the
input register has been changed since the last time the DAC
register was updated. This removes unnecessary crosstalk.
Clear Input ( CLR )
CLR is an active low, asynchronous clear that resets the input
and DAC registers.
Chip Select Input ( CS )
CS is an active low input that selects the device.
Write Input ( WR )
WR is an active low input that controls writing of data to the
device. Data is latched into the input register on the rising edge
of WR .
Read Input ( RD )
RD is an active low input that controls when data is read back
from the internal DAC registers. On the falling edge of RD , data
is shifted onto the data bus. Under the conditions of a high
capacitive load and high supplies, the user must ensure that the
dynamic current remains at an acceptable level, therefore
ensuring that the die temperature is within specification. The
die temperature can be calculated as
T
DIE
= T
AMBIENT
+ V
DD
( I
DD
+ I
DYNAMIC
)θ
JA
Rev. 0 | Page 17 of 24
where I
Load DAC Input ( LDAC )
LDAC transfers data from the input register to the DAC register,
and therefore updates the outputs. The LDAC function enables
double-buffering of the DAC data, GAIN data, and BUF. There
are two LDAC modes:
•
•
POWER-ON RESET
The AD5346/AD5347/AD5348 have a power-on reset function,
so that they power up in a defined state. The power-on state is
•
•
•
•
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
POWER-DOWN MODE
The AD5346/AD5347/AD5348 have low power consumption,
dissipating typically 2.4 mW with a 3 V supply and 5 mW with
a 5 V supply. Power consumption can be further reduced when
the DACs are not in use by putting them into power-down
mode, which is selected by taking the PD pin low.
When the PD pin is high, the DACs work normally with a typi-
cal power consumption of 1 mA at 5 V (0.8 mA at 3 V). In
power-down mode, however, the supply current falls to 400 nA
at 5 V (120 nA at 3 V) when the DACs are powered down. Not
only does the supply current drop, but the output stage is also
internally switched from the output of the amplifier, making it
open-circuit. This has the advantage that the outputs are three-
state while the part is in power-down mode, and provides a
defined input condition for whatever is connected to the outputs
of the DAC amplifiers. The output stage is illustrated in Figure 39.
Synchronous Mode. In this mode, the DAC register is
updated after new data is read in on the rising edge of the
WR input. LDAC can be tied permanently low or pulsed as
shown in Figure 3.
Asynchronous Mode. In this mode, the outputs are not
updated at the same time that the input register is written
to. When LDAC goes low, the DAC register is updated with
the contents of the input register.
Normal operation
Reference input buffered
0 V to V
Output voltage set to 0 V
DYNAMIC
REF
Figure 39. Output Stage During Power-Down
=
STRING DAC
RESISTOR
output range
cvf and
c = capacitance or the data bus
v = V
f = readback frequency
DD
AD5346/AD5347/AD5348
AMPLIFIER
POWER-DOWN
CIRCUITRY
V
OU T