AD9742 Analog Devices, AD9742 Datasheet - Page 18

• Manufacturer Part Number: AD9742
• Manufacturer: Analog Devices

Specifications of AD9742

• Resolution (bits): 12bit
• Dac Update Rate: 210MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

AD9742
Note that the ratio in Figure 36 is calculated as amps out/volts
in. Noise on the analog power supply has the effect of modulat-
ing the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, will be added in a nonlinear
manner to the desired IOUT. Due to the relative different size
of these switches, the PSRR is very code dependent. This can
produce a mixing effect that can modulate low frequency power
supply noise to higher frequencies. Worst-case PSRR for either
one of the differential DAC outputs will occur when the full-
scale current is directed toward that output. As a result, the
PSRR measurement in Figure 36 represents a worst-case condi-
tion in which the digital inputs remain static and the full-scale
output current of 20 mA is directed to the DAC output being
measured.
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplic-
ity’s sake (ignoring harmonics), all of this noise is concentrated
at 250 kHz. To calculate how much of this undesired noise will
85
80
75
70
65
60
55
50
45
40
0
Figure 36. Power Supply Rejection Ratio (PSRR)
2
4
FREQUENCY (MHz)
6
8
10
12
Rev. B | Page 18 of 32
appear as current noise superimposed on the DAC’s full-scale
current, I
at 250 kHz. To calculate the PSRR for a given R
units of PSRR are converted from A/V to V/V, adjust the curve in
Figure 36 by the scaling factor 20 Ω log (R
R
at 250 kHz, which is 85 dB in Figure 36, becomes 51 dB V
Proper grounding and decoupling should be a primary objec-
tive in any high speed, high resolution system. The AD9742
features separate analog and digital supplies and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, AVDD, the analog supply, should be
decoupled to ACOM, the analog common, as close to the chip
as physically possible. Similarly, DVDD, the digital supply,
should be decoupled to DCOM as close to the chip as physically
possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 37. The circuit con-
sists of a differential LC filter with separate power supply and
return lines. Lower noise can be attained by using low ESR type
electrolytic and tantalum capacitors.
TTL/CMOS
LOAD
CIRCUITS
LOGIC
POWER SUPPLY
is 50 Ω, the PSRR is reduced by 34 dB (i.e., PSRR of the DAC
Figure 37. Differential LC Filter for Single 3.3 V Applications
OUTFS
3.3V
, one must determine the PSRR in dB using Figure 36
FERRITE
BEADS
100µF
ELECT.
LOAD
10µF–22µF
TANT.
). For instance, if
LOAD
, such that the
0.1µF
CER.
OUT
/V
AVDD
ACOM
IN
).