AD9772A Analog Devices, AD9772A Datasheet - Page 21

• Manufacturer Part Number: AD9772A
• Manufacturer: Analog Devices

Specifications of AD9772A

• Resolution (bits): 14bit
• Dac Update Rate: 160MSPS
• Dac Settling Time: 11ns
• Max Pos Supply (v): +3.6V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: Par

differential clock input should be driven with a reference clock
that is twice the data input rate in baseband applications, or that
is four times the data input rate in direct IF applications in
which the quarter-wave mixing option is employed (that is,
MOD1 and MOD0 active high). The clock distribution circuitry
remains enabled, providing a 1× internal clock at PLLLOCK.
Digital input data is latched into the AD9772A on every other
rising edge of the differential clock input. The rising edge that
corresponds to the input latch immediately precedes the rising
edge of the 1× clock at PLLLOCK. Adequate setup and hold
times for the input data, as shown in Figure 3, should be
allowed. Note that enough delay is present between
CLK+/CLK− and the data input latch to cause the minimum
setup time for input data to be negative. This is noted in the
Digital Filter Specifications section. PLLLOCK contains a
relatively weak driver output, with its output delay (t
sensitive to output capacitance loading. Therefore, PLLLOCK
should be buffered for fanouts greater than 1 and/or for load
capacitance greater than 10 pF. If a data timing issue exists
between the AD9772A and its external driver device, the
1× clock appearing at PLLLOCK can be inverted via an external
gate to ensure proper setup and hold time.
SYNCHRONIZATION OF CLOCK/DATA USING
RESET WITH PLL DISABLED
The relationship between the internal and external clocks in
this mode is shown in Figure 34. A clock at the output update
data rate (2× the input data rate) must be applied to the CLK+
and CLK− inputs. Internal dividers create the internal 1× clock
necessary for the input latches. With the PLL disabled, a delayed
version of the 1× clock is present at the PLLLOCK pin. The
DAC latch is updated on the rising edge of the external 2× clock
that corresponds to the rising edge of the 1× clock. Updates to
the input data should be synchronized to this rising edge as
shown in Figure 34. To ensure this synchronization, a Logic 1
should be momentarily applied to the RESET pin on power-up
before CLK+/CLK− is applied. Momentarily applying a Logic 1
to the RESET pin brings the 1× clock at PLLLOCK to a Logic 1.
On the next rising edge of the 2× clock, the 1× clock goes to
CLKCOM
CLKVDD
OUT1×
Figure 33. Clock Multiplier with PLL Clock Multiplier Disabled
MOD1 MOD0 RESET
PLLLOCK
DISTRIBUTION
CLOCK
CLK+
+
CLOCK CONTROL
CLK–
–
PRESCALER
DIV1
DETECTOR
EXT/INT
PHASE
DIV0
AD9772A
CHARGE
PUMP
VCO
PLLCOM
OD
)
PLLVDD
LPF
Rev. C | Page 21 of 40
Logic 0. The following rising edge of the 2× clock causes the 1×
clock to go to Logic 1 again and updates the data in both of the
input latches.
Figure 35 and Figure 36 illustrate the details of the RESET
function timing. The RESET pin going from a high to a low
logic level enables the 1× clock output generated by the
PLLLOCK pin. If RESET goes low before the rising edge of the
2× clock as shown in Figure 35, PLLLOCK goes high on the
following edge of the 2× clock. If RESET goes from a high to a
low logic level 600 ps or later following the rising edge of the 2×
clock, as shown in Figure 36, there is a delay of one 2× clock
cycle before PLLLOCK goes high. In either case, as long as
RESET remains low, PLLLOCK changes state on every rising
edge of the 2× clock. As previously stated, the rising edge of the
2× clock immediately preceding the rising edge of PLLLOCK
latches data into the AD9772A input latches.
DELAYED INTERNAL
DELAYED 1× CLOCK
LOAD-DEPENDENT,
DIGITAL DATA IN
Figure 36. RESET Timing with PLL Disabled and Insufficient Setup Time
I
OUTA
2
3
AT PLLLOCK
2
3
1
1
EXTERNAL
CH1
CH3 2.00VΩ
CH1 2.00VΩ CH2 2.00VΩ M 10.0ns CH3 2.00VΩ
2× CLOCK
1× CLOCK
Figure 34. Internal Timing of AD9772A with PLL Disabled
OR I
T
T
T
T
T
T
2.00VV
OUTB
Figure 35. RESET Timing with PLL Disabled
CH2
DATA
2.00VV
t
D
[ T
[ T
t
LPW
M 10.0ns CH4
]
]
t
PD
1.20V
DATA ENTERS INPUT
LATCHES ON THIS EDGE
PLLLOCK
EXTERNAL
1× CLOCK
RESET
EXTERNAL
2× CLOCK
RESET
PLLLOCK
AD9772A
t
PD