AD5313 Analog Devices, AD5313 Datasheet - Page 19

• Manufacturer Part Number: AD5313
• Description: 2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 10-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD5313

• Resolution (bits): 10bit
• Dac Update Rate: 143kSPS
• Dac Settling Time: 7µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

POWER-DOWN MODES
The AD5303/AD5313/AD5323 have very low power consump-
tion, dissipating only 0.7 mW with a 3 V supply and 1.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bit 13 and Bit 12
(PD1 and PD0) of the control word. Table 7 shows how the
state of the bits corresponds to the mode of operation of that
particular DAC.
Table 7. PD1/PD0 Operating Modes
PD1
0
0
1
1
When both bits are set to 0, the DACs work normally with their
normal power consumption of 300 μA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V) when both DACs are powered down. Not
only does the supply current drop, but the output stage is also
internally switched from the output of the amplifier to a resistor
network of known values. This has the advantage that the
output impedance of the part is known while the part is in
power-down mode and provides a defined input condition
for whatever is connected to the output of the DAC amplifier.
PD0
0
1
0
1
Operating Mode
Normal operation
Power-down (1 kΩ load to GND)
Power-down (100 kΩ load to GND)
Power-down (high impedance output)
Rev. B | Page 19 of 28
There are three different power-down options. The output is
connected internally to GND through either a 1 kΩ resistor or
a 100 kΩ resistor, or it is left in a high impedance state (three-
state). The output stage is illustrated in Figure 34.
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 μs for V
V
The software power-down modes programmed by PD0 and
PD1 are overridden by the PD pin. Taking this pin low puts
both DACs into power-down mode simultaneously and both
outputs are put into a high impedance state. If PD is not used,
it should be tied high.
DD
= 3 V (see Figure 24 for a plot).
STRING DAC
RESISTOR
Figure 34. Output Stage During Power-Down
POWER-DOWN
CIRCUITRY
AMPLIFIER
AD5303/AD5313/AD5323
DD
= 5 V and 5 μs when
RESISTOR
NETWORK
V
OUT