AD5323 Analog Devices, AD5323 Datasheet - Page 22

• Manufacturer Part Number: AD5323
• Description: 2.5 V to 5.5 V, 230 µA, Dual Rail-to-Rail Voltage Output 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of AD5323

• Resolution (bits): 12bit
• Dac Update Rate: 125kSPS
• Dac Settling Time: 8µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5303/AD5313/AD5323
OPTO-ISOLATED INTERFACE FOR PROCESS
CONTROL APPLICATIONS
The AD5303/AD5313/AD5323 has a versatile 3-wire serial
interface making it ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements, or distance, it may be necessary to isolate the
AD5303/AD5313/AD5323 from the controller. This can easily
be achieved by using opto-isolators, which provides isolation
in excess of 3 kV. The serial loading structure of the AD5303/
AD5313/AD5323 makes it ideally suited for use in opto-isolated
applications. Figure 42 shows an opto-isolated interface to the
AD5303/AD5313/AD5323 where DIN, SCLK, and SYNC are
driven from opto-couplers. The power supply to the part also
needs to be isolated. This is done by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5303/AD5313/AD5323.
DECODING MULTIPLE AD5303/AD5313/AD5323s
The SYNC pin on the AD5303/AD5313/AD5323 can be used
in applications to decode a number of DACs. In this application,
all the DACs in the system receive the same serial clock and
serial data, but only the SYNC to one of the devices is active at
any one time, allowing access to two channels in this 8-channel
system. The 74HC139 is used as a 2-to-4 line decoder to address
any of the DACs in the system. To prevent timing errors from
occurring, the enable input should be brought to its inactive
state while the coded address inputs are changing state.
Figure 43 shows a diagram of a typical setup for decoding
multiple AD5303/AD5313/AD5323 devices in a system.
POWER
SCLK
SYNC
DIN
Figure 42. AD5303/AD5313/AD5323 in an Opto-Isolated Interface
10kΩ
10kΩ
10kΩ
REGULATOR
V
V
V
DD
DD
DD
5V
AD5303/AD5313/
SCLK
SYNC
DIN
GND BUF A BUF B
AD5323
V
DD
V
V
V
V
OUT
REF
OUT
REF
10µF
A
B
A
B
0.1µF
Rev. B | Page 22 of 28
AD5303/AD5313/AD5323 AS A DIGITALLY
PROGRAMMABLE WINDOW DETECTOR
A digitally programmable upper/lower limit detector using
the two DACs in the AD5303/AD5313/AD5323 is shown in
Figure 44. The upper and lower limits for the test are loaded
to DAC A and DAC B, which, in turn, set the limits on the
CMP04. If the signal at the V
grammed window, an LED indicates the fail condition.
Figure 43. Decoding Multiple AD5303/AD5313/AD5323 Devices in a System
SYNC
SCLK
ADDRESS
V
ENABLE
DIN
REF
CODED
5V
SCLK
Figure 44. Window Detector Using AD5303/AD5313/AD5323
DIN
0.1µF
V
V
SYNC
DIN
SCLK
AD5303/AD5313/
REF
REF
1G
1A
1B
A
B
AD5323
74HC139
10µF
GND
DGND
V
V
DD
CC
V
V
V
DD
OUT
OUT
1Y0
1Y1
1Y2
1Y3
A
B
IN
V
IN
input is not within the pro-
CMP04
1/2
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
SYNC
DIN
SCLK
PASS/FAIL
1kΩ
1/6 74HC05
FAIL
AD5303/
AD5313/
AD5323
AD5303/
AD5313/
AD5323
AD5303/
AD5313/
AD5323
AD5303/
AD5313/
AD5323
1kΩ
PASS