ADM697 Analog Devices, ADM697 Datasheet - Page 7

• Manufacturer Part Number: ADM697
• Manufacturer: Analog Devices

Specifications of ADM697

• Product Description: µP Supv with CE Inputs, Adj Low Line V Monitor, Adj W-dog Timer, Low Line, Pwr Fail & W-dog Status
• Reset Threshold (v): 1.3,Adjustable
• Min Reset Timeout (ms): 35
• Reset Output-stage: Active-High/Push-Pull,Active-Low/Push-Pull
• Backup-battery Switch: No
• Chip Enable Gating: Yes
• Typ Watchdog Timeout (ms): 100,1600,adj.
• Package: DIP,SOIC
• Us Price 1000-4999: n/a
• Display In Ist: Yes
• Batt Source Sel Flg: Y
• Reset Threshold Summary: 1.3V (Adjustable)
• Min Positive Supply (v): +3V
• Batt-backup-flg: Yes

REV. 0
CE Gating and RAM Write Protection (ADM697)
The ADM697 contains memory protection circuitry which
ensures the integrity of data in memory by preventing write
operations when LL
LL
with a 5 ns propagation delay. When LL
threshold, an internal gate forces CE
CE
CE
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V
valid level.
If the 5 ns typical propagation delay of CE
nect CE
high speed external logic gate.
Power Fail Warning Comparator
An additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power
LOW LINE
IN
IN
OUT
RESET
CE
.
CE
LL
is greater than 1.3 V, CE
OUT
IN
IN
typically drives the CE, CS, or Write input of battery
IN
t
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
1
to GND and use the resulting CE
= RESET TIME
V2
CE
Figure 6. Chip Enable Timing
Figure 5. Chip Enable Gating
IN
t
IN
1
LL
LL
is below the threshold voltage. When
IN
IN
LOW = 0
OK = 1
ADM697
V1
OUT
is a buffered replica of CE
OUT
V2
IN
high, independent of
OUT
falls below the 1.3 V
t
1
OUT
CE
is excessive, con-
OUT
to control a
CC
is at an in-
IN
V1
,
–7–
Fail Output (PFO) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. The voltage divider ratio
can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the +5 V power supply falls below
the reset threshold. PFO is normally used to interrupt the
microprocessor so that data can be stored in RAM and the shut-
down procedure executed before power is lost.
Signal
V
RESET
RESET
LOW LINE
BATT ON
WDI
WDO
PFI
PFO
CE
CE
OSC IN
OSC SEL
Table II. Input and Output Status In Battery Backup Mode
OUT
IN
OUT
POWER
INPUT
R1
R2
Figure 7. Power Fail Comparator
Status
(ADM696) V
internal PMOS switch.
Logic low.
Logic high. The open circuit output voltage is
equal to V
Logic low.
(ADM696) Logic high. The open circuit voltage
is equal to V
WDI is ignored. It is internally disconnected
from the internal pullup resistor and does not
source or sink current as long as its input voltage
is between GND and V
does not affect supply current.
Logic high. The open circuit voltage is equal to
V
The Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
Logic low.
CE
from its internal pullup and does not source or
sink current as long as its input voltage is be-
tween GND and V
not affect supply current.
Logic high. The open circuit voltage is equal to
V
OSC IN is ignored.
OSC SEL is ignored.
OUT
OUT
POWER
IN
INPUT
.
.
FAIL
is ignored. It is internally disconnected
OUT
OUT
ADM69x
OUT
.
1.3V
.
ADM696/ADM697
is connected to V
OUT
. The input voltage does
OUT
. The input voltage
PFO
POWER
FAIL
OUTPUT
BATT
via an