ADUC831 Analog Devices, ADUC831 Datasheet
ADUC831
Specifications of ADUC831
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ADUC831 Summary of contents
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... Runs from 1 MHz–16 MHz to external crystal. The ADuC832 is also available. Functionally is the same as the ADuC831, except the ADuC832 runs from a 32 kHz external crystal with on-chip PLL. MicroConverter is a registered trademark and QuickStart is a trademark of Analog Devices, Inc ...
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... ULOAD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Flash/EE Program Memory Security . . . . . . . . . . . . . . . . 28 Using the Flash/EE Data Memory . . . . . . . . . . . . . . . . . . 29 ECON—Flash/EE Memory Control SFR . . . . . . . . . . . . 29 Flash/EE Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . 30 ADuC831 CONFIGURATION REGISTER (CFG831 USER INTERFACE TO OTHER ON-CHIP ADuC831 PERIPHERALS . . . . . . . . . . . . . . . . . . . . . 32 Using the DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Pulsewidth Modulator (PWM Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . Compatible Interface . . . . . . . . . . . . . . . . . . . . . . . . . 40 Dual Data Pointer ...
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... LSB typ mV max V Range REF % max AV Range DD % typ V Range REF % typ % of Full Scale on DAC1 V typ DAC V = 2.5 V REF V typ DAC REF DD Ω typ µs typ Full-Scale Settling Time to within 1/2 LSB of Final Value nV sec typ 1 LSB Change at Major Carry ADuC831 SAMPLE ...
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... ADuC831 SPECIFICATIONS (continued) Parameter DAC CHANNEL SPECIFICATIONS Internal Buffer Disabled 10 DC ACCURACY Resolution Relative Accuracy 11 Differential Nonlinearity Offset Error Gain Error 4 Gain Error Mismatch ANALOG OUTPUTS Voltage Range_0 REFERENCE INPUT/OUTPUT 14 REFERENCE OUTPUT Output Voltage (V ) REF Accuracy Power Supply Rejection Reference Temperature Coefficient ...
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... ADuC831 Test Conditions/Comments µA I SOURCE µA I SOURCE I = 1.6 mA SINK I = 1.6 mA SINK I ...
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... ADuC831 SPECIFICATIONS (continued) Parameter 19, 20 POWER REQUIREMENTS Power Supply Voltages AV /DV to AGND DD DD Power Supply Currents Normal Mode DV Current DD AV Current DD DV Current DD AV Current DD Power Supply Currents Idle Mode DV Current DD AV Current Current DD AV Current DD Power Supply Currents Power Down Mode ...
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... Digital Output Voltage to DGND . . . –0 AGND . . . . . . . . . . . . . . . . . –0 REF Analog Inputs to AGND . . . . . . . . . . –0 Operating Temperature Range Industrial ADuC831BS . . . . . . . . . . . . . . . . . . . . . . –40°C to +125°C Operating Temperature Range Industrial ADuC831BCP . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C θ ...
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... ADC0 T/H ADC1 ... MUX ... ADC6 ADC7 TEMP SENSOR BAND GAP REFERENCE V BUF REF C REF Figure 1. ADuC831 Block Diagram (Shaded areas are features not present on the ADuC812) PIN CONFIGURATION P2.7/PWM1/A15/A23 P1.1/ADC1/T2EX 39 P1.2/ADC2 P2.6/PWM0/A14/A22 38 P1.3/ADC3 P2.5/A13/A21 37 AV P2.4/A12/A20 36 AV DGND 35 AGND ...
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... REV. 0 PIN FUNCTION DESCRIPTIONS 2 C Compatible or SPI Data Input/Output Pin 2 C Compatible or SPI Serial Interface Clock –9– ADuC831 ...
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... ADuC831 Mnemonic Type Function PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor on power-up or RESET ...
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... V very tight code distribution of 1 LSB with the majority of codes appearing in one output bin. TPC 11 and TPC 12 show typical FFT plots for the ADuC831. These plots were generated using an external clock input. The ADC is using its internal reference (2.5 V) sampling a full-scale, 10 kHz sine wave test tone input at a sampling rate of 149 ...
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... ADuC831 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 511 1023 1535 2047 2559 ADC CODES TPC 5. Typical DNL Error, V 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 511 1023 1535 2047 2559 ADC CODES TPC 6. Typical DNL Error, V 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0.5 1.0 1.5 2.0 EXTERNAL REFERENCE – V TPC 7 ...
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... DD 0. 152kHz S –75 SNR 0.70 –80 0.65 0.60 –85 THD 0.55 –90 0.50 –95 0.45 0.40 –100 2.5 5 TPC 16. Typical Temperature Sensor Output vs. REF, DD Temperature –13– ADuC831 AV / 152kHz S SNR 0.5 1.0 1.5 2.0 2.5 3.0 EXTERNAL REFERENCE – 92.262 119.05 145.83 172.62 199.41 65.476 FREQUENCY – kHz ...
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... ADuC812, where code execution can overflow from the internal code space to external code space once the PC becomes greater than 1FFFH, the ADuC831 does not support the rollover from F7FFH in internal code space to F800H in external code space. Instead the 2048 bytes between F800H and FFFFH will appear as NOP instructions to user code ...
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... MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. The ADuC831, however, can access MBytes of external data memory. This is an enhancement of the 64 kBytes external data memory space available on a standard 8051 compatible core. ...
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... DPH, DPL), although INC DPTR instructions will automatically carry over to DPP three independent 8-bit registers (DPP, DPH, DPL). The ADuC831 supports dual data pointers. Refer to the Dual Data Pointer section. Program Status Word (PSW) The PSW SFR contains several bits reflecting the current status of the CPU as detailed in Table I ...
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... FFH 81H 07H THESE BITS ARE CONTAINED IN THIS BYTE. TCON IT0 IE0 89H 0 88H 0 88H 00H –17– ADuC831 '1' in the figure below, i.e., the bit DAC0H DAC1L DAC1H DACCON RESERVED FAH 00H FBH 00H FCH 00H FDH 04H 3 3 ...
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... MCU core. This automatic capture facility can extend through a 16 MByte external data memory space. The ADuC831 is shipped with factory programmed calibration coefficients that are automatically downloaded to the ADC on power-up ensuring optimum ADC performance. The ADC core contains internal offset and gain calibration registers, that can be hardware calibrated to minimize system errors ...
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... The external trigger enable bit (EXC) is set by the user to allow the external Pin P3.5 (CONVST used as the active low convert start input. This input should be an active low pulse (minimum pulsewidth >100 ns) at the required sample rate. REV. 0 Table III. ADCCON1 SFR Bit Designations –19– ADuC831 ...
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... ADuC831 ADCCON2 – (ADC Control SFR #2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address: D8H SFR Power-On Default Value: 00H Bit Addressable: YES Name Description Bit ADCCON2.7 ADCI The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion ...
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... Set to 1 for Gain Calibration. ADCCON3.0 SCAL Start Calibration Cycle Bit. When set, this bit starts the selected calibration cycle automatically cleared when the calibration cycle is completed. REV. 0 Table V. ADCCON3 SFR Bit Designations AVGS0 Number of Averages –21– ADuC831 ...
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... The Schottky diodes in Figure 10 may be necessary to limit the voltage applied to the analog input pin as per the data sheet absolute maximum ratings. They are not necessary if the op amp is powered from the same supply as the ADuC831 since in that case the op amp is unable to generate voltages above V or below ground ...
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... ADC. The ADuC831 powers up with its internal voltage reference in the “on” state. This is available at the V before there will be a gain error between this and that of the ADC ...
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... This mode allows the ADuC831 to capture a contiguous sample stream at full ADC update rates (247 kHz). A Typical DMA Mode Configuration Example To set the ADuC831 into DMA mode a number of steps must be followed: 1. The ADC must be powered down. This is done by ensuring MD1 and MD0 are both set ADCCON1. ...
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... REV. 0 ADC Offset and Gain Calibration Coefficients The ADuC831 has two ADC calibration coefficients, one for offset calibration and one for gain calibration. Both the offset and gain calibration coefficients are 14-bit words, and are each stored in two registers located in the Special Function Register (SFR) area ...
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... ADuC831 INITIATING CALIBRATION IN CODE When calibrating the ADC, using ADCCON1 the ADC should be set up into the configuration in which it will be used. The ADCCON3 register can then be used to set the device up and calibrate the ADC offset and gain. MOV ADCCON1,#08CH ;ADC on; ADCCLK set ...
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... ADuC831 Flash/EE Memory Reliability The Flash/EE program and data memory arrays on the ADuC831 are fully qualified for two key Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention ...
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... Figure 19. ULOAD mode can be used to upgrade your code in the field via any user defined download protocol. Configuring the SPI port on the ADuC831 as a slave possible to completely repro- gram the 56 kBytes of Flash/EE program memory in only 5 seconds (see uC007). ...
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... USING THE FLASH/EE DATA MEMORY The 4 kBytes of Flash/EE data memory is configured as 1024 pages, each of four bytes. As with the other ADuC831 peripherals, the interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–4) are used to hold the four bytes of data at each page. The page is addressed via the two registers EADRH and EADRL ...
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... WRITEBYTE (1 byte) It should be noted that a given mode of operation is initiated as soon as the command word is written to the ECON SFR. The core microcontroller operation on the ADuC831 is idled until the requested Program/Read or Erase mode is completed. In practice, this means that even though the Flash/EE memory mode of operation is typically initiated with a two-machine cycle MOV instruction (to write to the ECON SFR), the next instruc- tion will not be executed until the Flash/EE operation is complete ...
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... ADuC831 Configuration SFR (CFG831) The CFG831 SFR contains the necessary bits to configure the internal XRAM, EPROM controller, PWM output selection and frequency, DAC buffer, and the extended SP. By default it configures the user into 8051 mode, i.e., extended SP is disabled, internal XRAM is disabled. ...
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... A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC831 incorporates two 12-bit, voltage output DACs on-chip. Each has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. Each has two selectable ranges (the internal band gap 2 ...
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... The end point nonlinearities conceptually illustrated in Figure 22 get worse as a function of output loading. Most of the ADuC831’s data sheet specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 22 become larger ...
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... This means that if a zero output is desired during power-up or power-down transient conditions, then a pull-down resistor must be added to each DAC output. Assuming this resistor is in place, the DAC outputs will remain at ground potential whenever the DAC is disabled. –34– DAC0 ADuC831 DAC1 Figure 25. Buffering the DAC Outputs REV. 0 ...
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... PULSEWIDTH MODULATOR (PWM) The PWM on the ADuC831 is highly flexible PWM offering programmable resolution and input clock, and can be config- ured for any one of six different modes of operation. Two of these modes allow the PWM to be configured DAC with bits of resolution. A block diagram of the PWM is shown in Figure 26 ...
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... PWM0H/L sets the duty cycle of the PWM output waveform, as shown in the diagram below. PWM COUNTER Figure 27. ADuC831 PWM in Mode 1 MODE 2: Twin 8-Bit PWM In Mode 2, the duty cycle of the PWM outputs and the resolution of the PWM outputs are both programmable. The maximum resolution of the PWM output is eight bits ...
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... PWM0H/L = C000H 16-BIT 16-BIT 4MHz 16-BIT 0, 3/4, 1/2, 1/4, 0 16-BIT PWM1H/L = 4000H –37– ADuC831 PWM COUNTERS Figure 31. PWM Mode 5 down to 0–AV /2. For best results, this mode DD DD CARRY OUT AT P2 248 s ...
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... In order to configure this pin as a digital input, the bit must be cleared, e.g., CLR P1.5. This line is active low. Data is only received or transmitted in slave mode when the SS pin is low, allowing the ADuC831 to be used in single master, multislave SPI configurations. If CPHA = 1 then the SS input may be permanently pulled low. With CPHA = 0, the SS ...
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... SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the SS pin is not used in master mode. If the ADuC831 needs to assert the SS pin on an external slave device, a port digital output pin should be used. ...
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... C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Patent Rights to use the ADuC831 system, provided that the system conforms to the I of the on-chip SPI interface. Therefore, the user can only enable ...
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... After reset the ADuC831 defaults to hardware slave mode. The interface is enabled by clearing the SPE bit in SPICON. Slave mode is enabled by clearing the I2CM bit in I2CCON. The ADuC831 has a full hardware slave. In slave mode the I address is stored in the I2CADD register. Data received transmitted is stored in the I2CDAT register. REV ...
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... ADuC831 DUAL DATA POINTER The ADuC831 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON also includes some nice features such as automatic hardware post-increment and post-decrement as well as automatic data pointer toggle. ...
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... POWER SUPPLY MONITOR As its name suggests, the Power Supply Monitor, once enabled, monitors the DV supply on the ADuC831. It will indicate DD when any of the supply pins drops below one of four user- selectable voltage trip points, from 4. 4.39 V. For correct operation of the Power Supply Monitor function, AV must be equal to or greater than 2 ...
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... WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC831 enters an erroneous state, possibly due to a program- ming error or electrical noise. The watchdog function can be disabled by clearing the WDE (Watchdog Enable) bit in the Watchdog Control (WDCON) SFR ...
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... INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. If the ADuC831 is in power-down mode, again with TIC inter- rupt enabled, the TII bit will wake up the device and resume code execution by vectoring directly to the TIC interrupt service vector address at 0053H ...
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... ADuC831 INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates an interrupt if enabled. SFR Address ...
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... SFR bit definitions. Parallel I/O The ADuC831 uses four input/output ports to exchange data with external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations while others are multiplexed with alternate functions for the peripheral features on the device ...
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... ADuC831 In general-purpose I/O port mode, Port 2 pins that have 1s written to them are pulled high by the internal pull-ups (Figure 39) and, in that state, they can be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 pins with 0s written to them will drive a logic low output voltage (V sinking 1 ...
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... Reading the latch rather than the pin will return the correct value of 1. SDATA/ MOSI PIN Q4 Q3 –49– ADuC831 (Logical AND, e.g., ANL P1, A) (Logical OR, e.g., ORL P2, A) (Logical EX-OR, e.g., XRL P3, A) (Jump if Bit = 1 and Clear Bit, e.g., JBC P1.1, LABEL) (Complement Bit, e.g., CPL P3.0) (Increment, e.g., INC P2) (Decrement, e ...
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... ADuC831 Timers/Counters The ADuC831 has three 16-bit Timer/Counters: Timer 0, Timer 1, and Timer 2. The Timer/Counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing Timer/Counter functionality in soft- ware. Each Timer/Counter consists of two 8-bit registers THx and TLx ( and 2). All three can be configured to oper- ate either as timers or event counters. In “ ...
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... TH0 and TL0 Timer 0 high byte and low byte. SFR Address = 8CH, 8AH respectively. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8DH, 8BH respectively. REV. 0 Table XX. TCON SFR Bit Designations –51– ADuC831 ...
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... ADuC831 TIMER/COUNTER 0 AND 1 OPERATING MODES The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer 1. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit Timer/Counter with a divide-by-32 prescaler ...
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... TH2 and TL2 Timer 2, data high byte and low byte. SFR Address = CDH, CCH respectively. RCAP2H and RCAP2L Timer 2, Capture/Reload byte and low byte. SFR Address = CBH, CAH respectively. REV. 0 Table XXI. T2CON SFR Bit Designations –53– ADuC831 ...
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... ADuC831 Timer/Counter Operation Modes The following paragraphs describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XXII. Table XXII. T2CON Operating Modes RCLK (or) TCLK CAP2 TR2 16-Bit Autoreload Mode In Autoreload mode, there are two options, which are selected by bit EXEN2 in T2CON ...
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... Table XXIII. SCON SFR Bit Designations SM1 Selected Operating Mode 0 Mode 0: Shift Register, fixed baud rate (Core_Clk/2) 1 Mode 1: 8-bit UART, variable baud rate 0 Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32) 1 Mode 3: 9-bit UART, variable baud rate –55– ADuC831 ...
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... ADuC831 Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF ...
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... CONTROL TIMER 2 OVERFLOW TL2 TH2 (8 BITS) (8 BITS) TR2 RELOAD RCAP2L RCAP2H TIMER 2 EXF 2 INTERRUPT CONTROL EXEN2 Figure 53. Timer 2, UART Baud Rates –57– ADuC831 × 3 Baud Rate = ( / (Timer 2 Overflow Rate) × 65536 – RCAP H, RCAP RCAP2H RCAP2L Actual % Value ...
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... The high integer dividers in a UART block mean that high speed baud rates are not always possible using some particular crystals. For example, using a 12 MHz crystal, a baud rate of 115200 is not possible. To address this problem, the ADuC831 has added a dedicated baud rate timer (Timer 3) specifically for generating highly accurate baud rates. ...
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... INTERRUPT SYSTEM The ADuC831 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE Interrupt Enable Register IP Interrupt Priority Register IEIP2 Secondary Interrupt Enable Register IE Interrupt Enable Register SFR Address ...
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... MHz. Note: the Flash/EE memory may not program correctly at a clock frequency of less than 2 MHz. External Memory Interface In addition to its internal program and data memories, the ADuC831 can access kBytes of external program memory (ROM/ PROM/etc.) and MBytes of external data memory (SRAM). ...
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... It emits the low byte of the data pointer (DPL) A8–A15 as an address, which is latched by a pulse of ALE prior to data being placed on the bus by the ADuC831 (write operation the SRAM (read operation). Port 2 (P2) provides the data pointer page byte (DPP latched by ALE, followed by the data pointer high byte (DPH) ...
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... DD Connect the ground terminal of each of these capacitors directly to the underlying ground plane. Finally, it should also be noted that, at all times, the analog and digital ground pins on the ADuC831 must be referenced to the same system ground reference point. Power Consumption The currents consumed by the various sections of the ADuC831 are shown in Table XXXIII ...
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... ADuC831’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than the ADuC831 input pins. A value of 100 Ω or 200 Ω is usually suffi- cient to prevent high speed signals from coupling capacitively into the ADuC831 and affecting the accuracy of ADC conversions. ...
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... In fact, both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two different ways. Note that the serial port debugger is fully contained on the ADuC831 device, (unlike ROM monitor type debuggers) and therefore no external memory is needed to enable in-system debug sessions. ...
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... QuickStart Plus—Comprehensive development system These systems are described briefly below. QuickStart Development System The QuickStart Development System is an entry-level, low cost development tool suite supporting the ADuC831. The system consists of the following PC-based (Windows hardware and software development tools. Hardware: ADuC831 Evaluation Board and Serial Port Programming Cable ...
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... For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded V /V level occurs for Port0, ALE, PSEN outputs = 100 pF LOAD 4 ADuC831 Machine Cycle Time is nominally defined as MCLKIN/12. DV – 0.5V DD 0.45V ( 3 5.0 V 10%. All specifications ...
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... CK t – – 100 – – – 105 – – 105 LLIV t PLIV t PXIZ t PXIX INSTRUCTION (IN) t PHAX ADuC831 Figure ...
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... ADuC831 Parameter EXTERNAL DATA MEMORY READ CYCLE RD Pulsewidth t RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX RD Low to Valid Data In t RLDV Data and Address Hold after RD t RHDX Data Float after RD t RHDZ t ALE Low to Valid Data In ...
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... LLWL WLWH t AVWL t t QVWX LLAX t QVWH A0–A7 DATA A16–A23 A8–A15 Figure 72. External Data Memory Write Cycle –69– ADuC831 Variable Clock Min Max Unit Figure 6t – 100 – – – ...
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... ADuC831 Parameter UART TIMING (Shift Register Mode) t Serial Port Clock Cycle Time XLXL t Output Data Setup to Clock QVXH t Input Data Setup to Clock DVXH t Input Data Hold after Clock XHDX t Output Data Hold after Clock XHQX ALE (O) TxD (OUTPUT CLOCK) RxD (OUTPUT DATA) ...
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... CONDITION REV. 0 Min 4.7 4.0 0.6 100 0.6 0.6 1.3 t SUP MSB LSB t DSU t DHD SHD 1 2 SUP L 2 Figure 74 Compatible Interface Timing –71– ADuC831 Max Unit Figure µs 74 µs 74 µs 74 µs 74 µs 0.9 74 µs 74 µs 74 µs 74 300 ns 74 300 ACK ...
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... ADuC831 Parameter SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge DHD t Data Output Fall Time ...
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... MSB IN t DSU REV. 0 Min 100 100 DAV BITS 6–1 MSB BITS 6–1 t DHD Figure 76. SPI Master Mode Timing (CPHA = 0) –73– ADuC831 Typ Max Unit 330 ns 330 150 ...
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... ADuC831 Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SCLOCK Low Pulsewidth SL t SCLOCK High Pulsewidth SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data Input Hold Time after SCLOCK Edge ...
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... DSU REV. 0 Min 0 100 100 DAV BITS 6–1 MSB BITS 6–1 MSB IN t DHD Figure 78. SPI Slave Mode Timing (CPHA = 0) –75– ADuC831 Typ Max Unit ns 330 ns 330 ...
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... ADuC831 1.03 0.88 0.73 SEATING PLANE VIEW A 0.23 0.11 BSC SQ PIN 1 INDICATOR 1.00 12 MAX 0.90 0.80 0.25 REF SEATING PLANE OUTLINE DIMENSIONS 52-Lead Plastic Quad Flatpack [MQFP] (S-52) Dimensions shown in millimeters 14.15 13.90 SQ 2.45 13.65 MAX 39 40 7.80 TOP VIEW REF (PINS DOWN) PIN 0.65 BSC 2.10 7 2.00 0 1.95 0.10 MIN VIEW A COPLANARITY ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MO-112-AC-1 ...