ADUC834 Analog Devices, ADUC834 Datasheet - Page 35

• Manufacturer Part Number: ADUC834
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 62kB Flash + 16/24-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC834

• Mcu Core: 8052
• Mcu Speed (mips): 1
• Sram (bytes): 2304Bytes
• Gpio Pins: 34
• Adc # Channels: 4
• Other: PWM

Note that Figure 22 represents a transfer function in 0-to-V
mode only. In 0-to-V
nonlinearity would be similar, but the upper portion of the
transfer function would follow the “ideal” line right to the end,
showing no signs of endpoint linearity errors.
The endpoint nonlinearities conceptually illustrated in Figure 22
get worse as a function of output loading. Most of the ADuC834
data sheet specifications assume a 10 kΩ resistive load to
ground at the DAC output. As the output is forced to source or
sink more current, the nonlinear regions at the top or bottom
(respectively) of Figure 22 become larger. With larger current
demands, this can significantly limit output voltage swing.
Figures 23 and 24 illustrate this behavior. It should be noted
that the upper trace in each of these figures is only valid for an
output range selection of 0-to-AV
loading will not cause high-side voltage drops as long as the
reference voltage remains below the upper trace in the corre-
sponding figure. For example, if AV
the high-side voltage will not be affected by loads less than 5 mA.
But somewhere around 7 mA, the upper curve in Figure 24
drops below 2.5 V (V
the output will not be capable of reaching V
REV. A
V
V
DD
DD
Figure 22. Endpoint Nonlinearities Due to Amplifier
Saturation
–100mV
–50mV
100mV
50mV
0mV
Figure 23. Source and Sink Current Capability
with V
V
DD
5
4
3
2
1
0
0
000 Hex
REF
= AV
REF
REF
DD
SOURCE/SINK CURRENT – mA
) indicating that at these higher currents,
= 5 V
mode (with V
5
DAC LOADED WITH 0FFF HEX
DAC LOADED WITH 0000 HEX
DD
DD
. In 0-to-V
REF
= 3 V and V
10
< V
REF
DD
REF
.
), the lower
mode, DAC
REF
= 2.5 V,
15
FFF Hex
DD
–35–
For larger loads, the current drive capability may not be
sufficient. In order to increase the source and sink current
capability of the DAC, an external buffer should be added, as
shown in Figure 25.
The DAC output buffer also features a high impedance disable
function. In the chip’s default power-on state, the DAC is
disabled and its output is in a high impedance state (or “three-
state”) where they remain inactive until enabled in software.
This means that if a zero output is desired during power-up or
power-down transient conditions, a pull-down resistor must be
added to each DAC output. Assuming this resistor is in place,
the DAC output will remain at ground potential whenever the
DAC is disabled.
Figure 24. Source and Sink Current Capability
with V
4
3
1
0
0
Figure 25. Buffering the DAC Output
REF
ADuC834
DAC LOADED WITH 0FFF HEX
DAC LOADED WITH 0000 HEX
= V
DD
SOURCE/SINK CURRENT – mA
= 3 V
12
5
10
ADuC834
15