ADUC816 Analog Devices, ADUC816 Datasheet - Page 36

• Manufacturer Part Number: ADUC816
• Description: Precision Analog Microcontroller: 1MIPS 8052 MCU + 8kB Flash + Dual 16-Bit ADC + 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC816

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 4

Figures 23 and 24 show the NMR for 50 Hz and 60 Hz across
the full range of SF word, i.e., SF = 13 dec to SF = 255 dec.
ADC Chopping
Both ADCs on the ADuC816 implement a chopping scheme
whereby the ADC repeatability reverses its inputs. The deci-
mated digital output words from the Sinc
positive offset and negative offset term included.
As a result, a final summing stage is included in each ADC so that
each output word from the filter is summed and averaged with the
previous filter output to produce a new valid output result to be
written to the ADC data SFRs. In this way, while the ADC
throughput or update rate is as discussed earlier and illustrated
in Table VII, the full settling time through the ADC (or the time
to a first conversion result), will actually be given by 2 × t
The chopping scheme incorporated in the ADuC816 ADC results
in excellent dc offset and offset drift specifications and is
extremely beneficial in applications where drift, noise rejection,
and optimum EMI rejection are important factors.
–100
–110
–120
–100
–110
–120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
10
10
30
30
50
50
70
70
90
90
110
110
SF – Decimal
SF – Decimal
130
130
150 170 190 210
150 170 190 210
3
filters therefore have a
230 250
230 250
ADC
.
Calibration
The ADuC816 provides four calibration modes that can be pro-
grammed via the mode bits in the ADCMODE SFR detailed in
Table IV. In fact, every ADuC816 has already been factory
calibrated. The resultant Offset and Gain calibration coefficients
for both the primary and auxiliary ADCs are stored on-chip
in manufacturing-specific Flash/EE memory locations. At power-
on, these factory calibration coefficients are automatically
downloaded to the calibration registers in the ADuC816 SFR
space. Each ADC (primary and auxiliary) has dedicated calibration
SFRs, these have been described earlier as part of the general
ADC SFR description. However, the factory calibration values
in the ADC calibration SFRs will be overwritten if any one of
the four calibration options are initiated and that ADC is enabled
via the ADC enable bits in ADCMODE.
Even though an internal offset calibration mode is described
below, it should be recognized that both ADCs are chopped. This
chopping scheme inherently minimizes offset and means that an
internal offset calibration should never be required. Also, because
factory 5 V/25°C gain calibration coefficients are automatically
present at power-on, an internal full-scale calibration will only
be required if the part is being operated at 3 V or at temperatures
significantly different from 25°C.
The ADuC816 offers “internal” or “system” calibration facilities.
For full calibration to occur on the selected ADC, the calibration
logic must record the modulator output for two different input
conditions. These are “zero-scale” and “full-scale” points. These
points are derived by performing a conversion on the different
input voltages provided to the input of the modulator during
calibration. The result of the “zero-scale” calibration conversion
is stored in the Offset Calibration Registers for the appropri-
ate ADC. The result of the “full-scale” calibration conversion
is stored in the Gain Calibration Registers for the appropriate
ADC. With these readings, the calibration logic can calculate
the offset and the gain slope for the input-to-output transfer
function of the converter.
During an “internal” zero-scale or full-scale calibration, the
respective “zero” input and “full-scale” input are automatically
connected to the ADC input pins internally to the device. A
“system” calibration, however, expects the system zero-scale and
system full-scale voltages to be applied to the external ADC pins
before the calibration mode is initiated. In this way external ADC
errors are taken into account and minimized as a result of system
calibration. It should also be noted that to optimize calibration
accuracy, all ADuC816 ADC calibrations are carried out auto-
matically at the slowest update rate.
Internally in the ADuC816, the coefficients are normalized before
being used to scale the words coming out of the digital filter. The
offset calibration coefficient is subtracted from the result prior to
the multiplication by the gain coefficient. All ADuC816 ADC
specifications will only apply after a zero-scale and full-scale
calibration at the operating point (supply voltage/temperature)
of interest.
From an operational point of view, a calibration should be treated
like another ADC conversion. A zero-scale calibration (if required)
should always be carried out before a full-scale calibration. System
software should monitor the relevant ADC RDY0/1 bit in the
ADCSTAT SFR to determine end of calibration via a polling
sequence or interrupt driven routine.
REV. A