ADUC812 Analog Devices, ADUC812 Datasheet - Page 21

• Manufacturer Part Number: ADUC812
• Description: Precision Analog Microcontroller: 1.3MIPS 8052 MCU + 8kB Flash + 8-Ch 12-Bit ADC + Dual 12-Bit DAC
• Manufacturer: Analog Devices

Specifications of ADUC812

• Mcu Core: 8052
• Mcu Speed (mips): 1.3
• Sram (bytes): 256Bytes
• Gpio Pins: 34
• Adc # Channels: 8

USER INTERFACE TO OTHER ON-CHIP ADuC812
PERIPHERALS
The following section gives a brief overview of the various
peripherals also available on-chip. A summary of the SFRs used
to control and configure these peripherals is also given.
DAC
The ADuC812 incorporates two 12-bit voltage output DACs
on-chip. Each has a rail-to-rail voltage output buffer capable
DACCON
SFR Address
Power-On Default Value
Bit Addressable
DACxH/L
Function
SFR Address
Power-On Default Value
Bit Addressable
The 12-bit DAC data should be written into DACxH/L, right-justified such that DACL contains the lower eight bits, and the lower
nibble of DACH contains the upper four bits.
REV. E
Bit
7
6
5
4
3
2
1
0
M
O
D
E
Name
MODE
RNG1
RNG0
CLR1
CLR0
SYNC
PD1
PD0
R
N
G
1
Description
The DAC MODE bit sets the overriding operating mode for both DACs.
Set to “1” = 8-bit mode (Write eight Bits to DACxL SFR).
Set to “0” = 12-bit mode.
DAC1 Range Select Bit.
Set to “1” = DAC1 range 0–V
Set to “0” = DAC1 range 0–V
DAC0 Range Select Bit.
Set to “1” = DAC0 range 0–V
Set to “0” = DAC0 range 0–V
DAC1 Clear Bit.
Set to “0” = DAC1 output forced to 0 V.
Set to “1” = DAC1 output normal.
DAC0 Clear Bit.
Set to “0” = DAC1 output forced to 0 V.
Set to “1” = DAC1 output normal.
DAC0/1 Update Synchronization Bit.
When set to “1” the DAC outputs update as soon as DACxL SFRs are written. The user can
simultaneously update both DACs by first updating the DACxL/H SFRs while SYNC is “0.” Both
DACs will then update simultaneously when the SYNC bit is set to “1.”
DAC1 Power-Down Bit.
Set to “1” = Power-on DAC1.
Set to “0” = Power-off DAC1.
DAC0 Power-Down Bit.
Set to “1” = Power-on DAC0.
Set to “0” = Power-off DAC0.
DAC Data Registers
DAC data registers, written by user to update the DAC output.
DAC0L (DAC0 Data Low Byte)
DAC0H (DAC0 Data High Byte)
00H
No
DAC Control
No
R
Register
FDH
04H
N
G
0
Table VIII. DACCON SFR Bit Designations
C
L
R
DD
DD
REF
REF
1
.
.
.
.
–21–
➝
➝
➝
➝
F9H; DAC1L (DAC1 data low byte)
FAH; DAC1H(DAC1 data high byte)
All four registers
All four registers
of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to
V
Each can operate in 12-bit or 8-bit mode. Both DACs share a
control register, DACCON, and four data registers, DAC1H/L,
DAC0H/L. It should be noted that in 12-bit asynchronous mode,
the DAC voltage output will be updated as soon as the DACL
data SFR has been written; therefore, the DAC data registers
should be updated as DACH first, followed by DACL.
REF
C
L
R
(the internal band gap 2.5 V reference) and 0 V to AV
0
S
Y
N
C
P
➝
➝
D
FBH
1
FCH
ADuC812
P
D
0
DD
.