ADUC7060 Analog Devices, ADUC7060 Datasheet - Page 60

• Manufacturer Part Number: ADUC7060
• Description: Low-Power, Precision Analog Microcontroller, Dual ?-? ADCs, Flash/EE, ARM7TDMI
• Manufacturer: Analog Devices

Specifications of ADUC7060

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 10
• Sram (bytes): 4096Bytes
• Gpio Pins: 14
• Adc # Channels: 10
• Other: 14 Bit DAC,PWM

ADuC7060/ADuC7061
IRQCLR Register
Name:
Address:
Default value:
Access:
IRQSTA
IRQSTA is a read-only register that provides the current
enabled IRQ source status (effectively a logic AND of the
IRQSIG and IRQEN bits). When set to 1, that source generates
an active IRQ request to the ARM7TDMI core. There is no
priority encoder or interrupt vector generation. This function is
implemented in software in a common interrupt handler
routine.
IRQSTA Register
Name:
Address:
Default value:
Access:
FAST INTERRUPT REQUEST (FIQ)
The fast interrupt request (FIQ) is the exception signal to enter
the FIQ mode of the processor. It is provided to service data
transfer or communication channel tasks with low latency. The
FIQ interface is identical to the IRQ interface and provides the
second level interrupt (highest priority). Four 32-bit registers
are dedicated to FIQ: FIQSIG, FIQEN, FIQCLR, and FIQSTA.
Bit 31 to Bit 1 of FIQSTA are logically OR’ e d to create the FIQ
signal to the core and to Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN clears, as a side effect, the same bit in IRQEN.
Likewise, a bit set to 1 in IRQEN clears, as a side effect, the
same bit in FIQEN. An interrupt source can be disabled in both
IRQEN and FIQEN masks.
FIQSIG
FIQSIG reflects the status of the different FIQ sources. If a
peripheral generates an FIQ signal, the corresponding bit in
the FIQSIG is set; otherwise, it is cleared. The FIQSIG bits are
cleared when the interrupt in the particular peripheral is
cleared. All FIQ sources can be masked in the FIQEN MMR.
FIQSIG is read only.
IRQCLR
0xFFFF000C
0x00000000
Write only
IRQSTA
0xFFFF0000
0x00000000
Read only
Rev. C | Page 60 of 108
FIQSIG Register
Name:
Address:
Default value:
Access:
FIQEN
FIQEN provides the value of the current enable mask. When a
bit is set to 1, the corresponding source request is enabled
to create an FIQ exception. When a bit is set to 0, the corre-
sponding source request is disabled or masked, which does not
create an FIQ exception. The FIQEN register cannot be used to
disable an interrupt.
FIQEN Register
Name:
Address:
Default value:
Access:
FIQCLR
FIQCLR is a write-only register that allows the FIQEN register
to clear in order to mask an interrupt source. Each bit that is set
to 1 clears the corresponding bit in the FIQEN register without
affecting the remaining bits. The pair of registers, FIQEN and
FIQCLR, allows independent manipulation of the enable mask
without requiring an atomic read-modify-write.
FIQCLR Register
Name:
Address:
Default value:
Access:
FIQSTA
FIQSTA is a read-only register that provides the current enabled
FIQ source status (effectively a logic AND of the FIQSIG and
FIQEN bits). When set to 1, that source generates an active FIQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
FIQSIG
Undefined
Read only
FIQEN
0x00000000
Read and write
FIQCLR
0x00000000
Write only
0xFFFF0104
0xFFFF0108
0xFFFF010C