CS8420-DSZ Cirrus Logic Inc, CS8420-DSZ Datasheet - Page 87

• Manufacturer Part Number: CS8420-DSZ
• Description: IC CONV S/R DGTL AUDIO 28-SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-DSZ

• Applications: Digital Audio
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC
• Audio Control Type: Sample Rate Converter
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1729

DS245F4
16. PLL FILTER
16.1
16.2
16.2.1 General
General
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure
41 is a simplified diagram of the PLL in CS8420 devices. When the PLL is locked to an AES3 input stream,
it is updated at each preamble in the AES3 stream. This occurs at twice the sampling frequency, F
the PLL is locked to ILRCK, it is updated at F
There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is impor-
tant. For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown
in
stream to provide lock update information to the PLL. This results in the PLL being immune to data-depen-
dent jitter effects because the AES3 preambles do not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component changes.
If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL will
only track up to ±12.5% from the nominal center sample rate. The nominal center sample rate is the sample
rate that the PLL first locks onto upon application of an AES3 data stream or after enabling the CS8420
clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its
wide lock range mode and re-acquire a new nominal center sample rate.
External Filter Components
The PLL behavior is affected by the external filter component values.
ommended configuration of the two capacitors and one resistor that comprise the PLL filter. In
and
jitter attenuation curve, takes the shortest time to lock, and offers the best output jitter performance. The
component values shown in
ple rate to be 8 kHz, and increases the lock time of the PLL. Lock times are worst case for an Fsi transition
of 96 kHz.
Figure 44
INPUT
Table
and
20, the component values shown for the 32 to 96 kHz range have the highest corner frequency
Figure
and Charge Pump
Comparator
Phase
45. In addition, the PLL has been designed to use only the preambles of the AES3
÷N
Table 18
Figure 41. PLL Block Diagram
and
Table 20
S
so that the duty cycle of the input doesn’t affect jitter.
Cfilt
Rfilt
for the 8 to 96 kHz range allows the lowest input sam-
Crip
VCO
Figure 5 on page 12
RMCK
shows the rec-
CS8420
Table 19
S
. When
87