CS8420-CS Cirrus Logic Inc, CS8420-CS Datasheet
CS8420-CS
Specifications of CS8420-CS
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CS8420-CS Summary of contents
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... Target applications include CD-R, DAT, MD, DVD and VTR equipment, mixing consoles, digital audio transmis- sion equipment, high quality D/A and A/D converters, effects processors and computer audio systems. ORDERING INFO CS8420-CS CDB8420 RMCK RERR Sample Rate Converter AES3 C & ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS8420 2 ® C MODE ...
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... Power Supply, Grounding, and PCB layout ................................................................... 44 12.4 Synchronization of Multiple CS8420s ............................................................................ 45 12.5 Extended Range Sample Rate Conversion ................................................................... 45 13. SOFTWARE MODE - PIN DESCRIPTION ........................................................................... 46 14. HARDWARE MODES ........................................................................................................... 49 14.1 Overall Description ........................................................................................................ 49 14.1.1 Hardware Mode Definitions ............................................................................... 49 14.1.2 Serial Audio Port Formats ................................................................................. 49 14.2 Hardware Mode 1 Description ....................................................................................... 50 14 ...
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... Table 8. HW Mode 2 Serial Audio Port Format Selection ............................................................. 53 Table 9. Hardware Mode 2 Start-up Options................................................................................. 53 Table 10. Hardware Mode 3 Start-up Options............................................................................... 57 Table 11. Hardware Mode 4 Start-up Options............................................................................... 61 Table 12. Hardware Mode 5 Start-up Options............................................................................... 64 Table 13 COPY/C and ORIG pin function ....................................................................... 67 Table 14 Serial Audio Port Format Selection ..................................................................... Mode .................................................................................. 27 CS8420 DS245PP2 ...
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... Fsi Fso THD °C; VA ±5%) A Symbol Min Upsampling 0 Downsampling 0 - 0.5465*Fso 110 (Note 41/Fsi + 43/Fso gd (AGND, DGND = 0V, all voltages with respect Symbol VD+,VA+ VA+ VD+ (Note CS8420 Min Typ Max Units 120 128 - 108 kHz 8 - 108 kHz 0. -117 -112 -110 -107 dB - ...
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... IH -0 0.4 (VD ±10 ±15 200 - (VD+) - (VD+) - 0.7 0.4 - 0.4 0.7 Min Typ Max 200 - - 4.096 - 55.3 8 3.072 - 41.5 12 2.048 - 27.7 16 8.0 - 108.0 - 200 - 2.048 - 27.7 16 CS8420 Units °C °C Units Units s MHz ns MHz ns MHz ns kHz ps RMS % MHz ns ns DS245PP2 ...
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... ILRCK OLRCK (input) t lrckd ISCLK OSCLK (input) lmd SDIN SDOUT Figure 2. Audio Ports Slave Mode and Data I °C; VA Min Typ Max dpd smd lmd - sckw sckl sckh lrckd lrcks lrcks sckh sckl t sckw dpd ds dh Timing CS8420 Units ...
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... For f <1 MHz. sck CCLK CDIN CDOUT pF) L Symbol (Note 9) (Note 10) (Note 11) (Note 11 scl t sch t css dsu Figure 3. SPI Mode Timing (T Min Typ Max 6.0 sck t 1 csh css scl sch dsu 100 100 f2 t csh CS8420 = 25 °C; A Units MHz DS245PP2 ...
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... Repeated t high t hdst sud low hdd 2 Figure Mode Timing 2 ® C MODE (Note 12 pF) L Min Typ Max 100 scl t 4 buf 4 hdst t 4 low 4 high 4 sust hdd t 250 - - sud 300 f 4 susp Stop Start susp hdst t sust t r CS8420 = A Units kHz ...
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... TXN CS8420 ILRCK OLRCK ISCLK OSCLK SDIN SDOUT RMCK SDA/CDOUT OMCK AD0/CS SCL/CCLK AD1/CDIN INT EMPH U RERR RST TCBL H/S AGND FILT DGND RFILT CFILT CRIP CS8420 +5V Digital Supply AES3/ Cable SPDIF Interface Equipment 3-wire Serial Audio Input Device Microcontroller DS245PP2 ...
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... CS8420 is intended for 16, 20, and 24-bit applica- tions where the input sample rate is unknown known to be asynchronous to the system sample rate. On the input side of the CS8420, AES3 or a 3-wire serial format can be chosen. The output side pro- duces both AES3 and a 3-wire serial format ...
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... DATA I/O FLOW AND CLOCKING OPTIONS The CS8420 can be configured for nine connectiv- ity alternatives, called data flows. Each data flow has an associated clocking set-up. Figure 6 shows the data flow switching, along with the control reg- ister bits which control the switches; this drawing only shows the audio data paths for simplicity ...
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... Serial Sample Audio Rate Input Converter AES3 Encoder RXN AES3 & Driver Rx RXP PLL RMCK OMCK Data Flow Control Bits Clock Source Control Bits TXD1-0: OUTC SPD1-0: 00 INC: 0 SRCD: 0 RXD1-0: 01 CS8420 OLRCK OSCLK SDOUT TXP TXN OLRCK OSCLK SDOUT TXP TXN 13 ...
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... AES3 TXP Encoder & Driver TXN Data Flow Control Bits Figure 14. AES3 Input to Serial Audio Output Only TXP AES3 Encoder & Driver TXN CS8420 ILRCK SDOUT OSCLK OLRCK SDIN ISCLK Serial Serial Audio Audio Output Input AES3 AES3 Sample Rx & Encoder ...
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... In summary, there is no dithering mechanism on the input side of the CS8420, and care must be taken to ensure that no truncation occurs. Dithering is used internally where appropriate in- side the SRC block. ...
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... Figure 16 shows a selection of common input for- mats, along with the control bit settings. The clock- ing of the input section of the CS8420 may be derived from the incoming ILRCK word rate clock, using the on-chip PLL. The PLL operation is de- scribed in the AES receiver description on page 19 ...
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... See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit DS245PP2 Left LSB MSB Left LSB MSB Left MSB LSB SISF SIRES1/0 SIJUST 00+ X XX* Figure 16. Serial Audio Input Example Formats Right LSB Right LSB MSB Right MSB LSB SIDEL SISPOL CS8420 MSB MSB SILRPOL ...
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... See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit Figure 17. Serial Audio Output Example Formats 18 Left LSB MSB Left LSB MSB Left MSB LSB Left LSB SOSF SORES1/0 SOJUST Right LSB MSB Right LSB MSB Right MSB LSB Right MSB SODEL SOSPOL SOLRPOL CS8420 MSB LSB DS245PP2 ...
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... The nominal center sample rate is the sample rate that the PLL first locks onto upon application of an AES3 data stream, or after enabling the CS8420 clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return to its wide lock range mode, and re-ac- quire a new nominal center sample rate ...
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... Jitter Frequency (H z) Figure 20. Jitter Attenuation Characteristics of PLL with “fast” Filter Components -10 -20 -30 -40 -50 -60 1 1000 10000 100000 Figure 19. Jitter Attenuation Characteristics of PLL 10000 100000 CS8420 10 100 1000 10000 Jitter Frequency (H z) with “medium” Filter Components 100000 DS245PP2 ...
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... Error Reporting and Hold Function While decoding the incoming AES3 data stream, the CS8420 can identify several kinds of error, in- dicated in the Receiver Error register. The UN- LOCK bit indicates whether the PLL is locked to the incoming AES3 data. The V bit reflects the cur- rent validity bit status ...
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... Q-channel block, which may be read via the control port. 9.4 Non-Audio Auto Detection Since it is possible to convey non-audio data in an AES3 data stream important to know whether the incoming AES3 data stream is digital audio or not. This information is typically conveyed in channel status bit 1 (AUDIO), which is extracted CS8420 DS245PP2 ...
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... CS8420. The user can manipulate the contents of the internal storage with a micro- controller. The CS8420 will also run in one of sev- eral automatic modes. The Appendix: Channel Sta- tus and User Data Buffer Management (page 72) ...
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... In this “mono mode”, 2 AES3 cables are needed for stereo data transfer. The CS8420 offers mono mode oper- ation, both for the AES3 receiver and for the AES3 24 ...
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... A2 B2 AES3 B selected TRANSMITTER STEREO MODE 96kHz stereo 96kHz frame rate A AES3 B Transmitter OMCK (256, 384, or 512x 96kHz) TRANSMITTER MONO MODE 96kHz mono 48kHz frame rate A + AES3 B Transmitter OMCK (256, 384, or 512x 96kHz) TRANSMITTER TIMING Frame STEREO Frame MONO A1 B1 CS8420 ...
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... The control port has 2 modes: SPI and I CS8420 acting as a slave device. SPI mode is se- lected if there is a high to low transition on the AD0/CS pin, after the RST pin has been brought 2 high ...
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... MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of con- secutive registers. Each byte is separated by an ac- knowledge bit. The ACK bit is output from the CS8420 after each input byte is read, and is input to the CS8420 from the microcontroller after each transmitted byte. I Philips Semiconductors. ...
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... Sample Rate Ratio 31 - Reserved C-bit or U-bit Data Buffer 56 to 126 - Reserved 127 - Chip ID and version register Reserved registers must not be written to during normal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8420 MAP5 ...
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... AUX0 0 QCRC CCRC UNLOCK 0 QCRCM CCRCM UNLOCKM 0 0 BSEL CBMR SRR7 SRR6 SRR5 SRR4 ID3 ID2 ID1 ID0 CS8420 DITH INT1 INT0 MMR MMT MMTCS TXD0 SPD1 SPD0 OUTC INC RXD1 SIJUST SIDEL SISPOL SOJUST SODEL SOSPOL SOLRPOL OVRGR DETC EFTC ...
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... Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. This setting requires an external pull up resistor on the INT pin Reserved TCBLD Transmit Channel Status Block pin (TCBL) direction specifier 0 - TCBL is an input (default TCBL is an output MUTEAES DITH CS8420 INT1 INT0 TCBLD DS245PP2 ...
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... Use left channel input data for consecutive sub-frame outputs (default) 1- Use right channel input data for consecutive sub-frame outputs DS245PP2 HOLD0 RMCKF MMR operation, default) (normal stereo operation, default). mode, left or right is determined by MMTLR bit) B sub-frame slot (default) CS8420 MMT MMTCS MMTLR 31 ...
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... AES3 receiver 11 - Reserved SPD1 - SPD0 Serial Audio Output Port Data Source 00 - SRC output (default Serial Audio Input Port 10 - AES3 receiver 11 - Reserved SRCD Input Data Source for SRC 0 - Serial Audio Input Port (default AES3 Receiver AESBP TXD1 TXD0 CS8420 SPD1 SPD0 SRCD DS245PP2 ...
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... Reading and writing the U and C data buffers is not possible. Power consumption is low (default Normal part operation. This bit must be written to the 1 state to allow the CS8420 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1 ...
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... SDIN sampled on rising edges of ISCLK (default SDIN sampled on falling edges of ISCLK SILRPOL ILRCK clock polarity 0 - SDIN data is for the left channel when ILRCK is high (default SDIN data is for the right channel when ILRCK is high SIRES1 SIRES0 SIJUST CS8420 SIDEL SISPOL SILRPOL DS245PP2 ...
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... SDOUT transitions occur on falling edges of OSCLK (default SDOUT transitions occur on rising edges of OSCLK SOLRPOL OLRCK clock polarity 0 - SDOUT data is for the left channel when OLRCK is high (default SDOUT data is for the right channel when OLRCK is high DS245PP2 SORES1 SORES0 SOJUST CS8420 SODEL SOSPOL SOLRPOL 35 ...
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... Sample rate range exceeded indicator. Occurs if Fsi/Fso or Fso/Fsi exceeds 3. OVRGL Over-range indicator for left (A) channel SRC output. Occurs on internal over-range for left channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full-scale. OVRGR Over-range indicator for right (B) channel SRC output. Occurs on internal over-range for right channel data ...
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... These registers default to 00 Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved DS245PP2 VFIFO REUNLOCK DETU SREM OVRGLM OVRGRM SRE1 OVRGL1 OVRGR1 SRE0 OVRGL0 OVRGR0 CS8420 EFTU QCH UOVW DETCM EFTCM RERRM DETC1 EFTC1 RERR1 DETC0 EFTC0 RERR0 37 ...
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... These registers default to 00 Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved VFIFOM REUNLOCKM DETUM VFIFO1 REUNLOCK1 DETU1 VFIFO0 REUNLOCK0 DETU0 CS8420 EFTUM QCHM UOVWM EFTU1 QCH1 UOVW1 EFTU0 QCH0 UOVW0 DS245PP2 ...
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... SCMS generation indicator. This is decoded from the category code and the L bit Received data is 1st generation or higher 1 - Received data is original Note: COPY and ORIG will both be set the incoming data is flagged as professional the receiver is not in use. DS245PP2 AUX1 AUX0 PRO CS8420 AUDIO COPY ORIG 39 ...
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... RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio sample even when unmasked. This register defaults to 00 CCRC UNLOCK CCRCM UNLOCKM VM CS8420 CONF BIP PAR CONFM BIPM PARM DS245PP2 ...
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... Channel A information is output during control port reads when CAM is set to 0 (One Byte Mode Channel B information is displayed at the EMPH pin and in the receiver channel status register. Channel B information is output during control port reads when CAM is set to 0 (One Byte Mode) DS245PP2 BSEL CBMR DETCI CS8420 EFTCI CAM CHS 41 ...
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... INDEX MINUTE MINUTE MINUTE SECOND SECOND FRAME FRAME FRAME ZERO ZERO ZERO ABS MINUTE ABS MINUTE ABS SECOND ABS SECOND ABS FRAME ABS FRAME CS8420 2 1 UBM0 DETUI EFTUI 2 1 CONTROL CONTROL CONTROL TRACK TRACK TRACK INDEX INDEX INDEX MINUTE MINUTE ...
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... CS8420 I.D. and Version Register (127) (Read Only ID3 ID2 ID3-0 ID code for the CS8420. Permanently set to 0001 VER3-0 CS8420 revision level. Revision B is coded as 0001, Revision C is coded as 0011, Revision D is coded as 0100 DS245PP2 SRR5 SRR4 SRR3 ...
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... ISSUES 12.1 Reset, Power Down and Start-up Options When RST is low, the CS8420 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are mut- ed. When RST is high, the control port becomes operational and the desired settings should be load- ed into the control registers ...
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... CS8420 AES3 trans- mitters at the channel status block boundaries. One DS245PP2 CS8420 must have its TCBL set to master; the oth- ers must be set to slave TCBL. Alternatively, TCBL can be derived from some external logic, in which case all the CS8420 devices should be set to slave TCBL ...
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... Input section recovered master clock output. Will frequency of 128x or 256x the input sample rate (Fsi). FILT - PLL Loop Filter * An RC network should be connected between this pin and ground. Recommended schematic and component values are given in the Receiver section of this data sheet. 46 CS8420 DS245PP2 ...
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... This pin should be permanently tied to VD+ or DGND. RST - Reset Input * When RST is low, the CS8420 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase ...
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... SCL/CCLK is the serial control interface clock, and is used to clock control data bits into and out of the CS8420. 2 AD0/CS - Address Bit Control Port Chip Select (SPI) A falling edge on this pin puts the CS8420 into SPI control port mode. With no falling edge, the CS8420 2 defaults mode control port interface on the CS8420. ...
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... HARDWARE MODES 14.1 Overall Description The CS8420 has six hardware modes, which allow use of the device without using a micro-controller to access the device control registers and CS & U data. The flexibility of the CS8420 is necessarily limited in hardware mode. Various pins change function in hardware mode, and various data paths are also possible ...
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... VD+ DFC1 S/AES H/S Clocked by Clocked by Input Derived Clock Output Clock Sample Rate Converter C & U bit Data Buffer MUTE PRO/C COPY ORIG EMPH/U CS8420 Function - - - Serial Output Port is Slave - - - Serial Output Port is Master - - LO Mode1A: C transmitted data is copied from received data, U & received PRO, EMPH, AUDIO are visible ...
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... The EMPH/U pin reflects either the state of the EMPH channel status bits in the incoming AES3 type data stream the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. When indicating emphasis EMPH/U is low if the incoming data indicates 50/15 otherwise. DS245PP2 CS8420 s pre-emphasis and high 51 ...
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... TCBLD - Transmit Channel Status Block Direction Input Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input. TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. 52 ...
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... Input Derived Clock Output Clock Sample Rate Converter C & U bit Data Buffer LOCK SFMT1 SFMT0 COPY/C ORIG/U EMPH/V CUVEN TCBL CS8420 Function 0 Serial Input & Output Format IF1&OF1 1 Serial Input & Output Format IF2&OF2 0 Serial Input & Output Format IF3&OF3 1 Serial Input & Output Format IF4&OF3 ...
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... RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will frequency of 256x the input sample rate (Fsi). LOCK - PLL Lock Indicator Output LOCK low indicates that the PLL is locked. This is also a start-up option pin, and requires a pull-up or pull-down resistor. 54 CS8420 DS245PP2 ...
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... AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times ...
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... OSCLK DFC1 H/S SDOUT OLRCK ILRCK Serial Clocked by Audio Output Clock Output Sample Rate Converter C & U bit Data Buffer PRO/C COPY ORIG EMPH/U AUDIO/V TCBL CS8420 Output Clock Source ISCLK SDIN OMCK Serial Audio Input AES3 TXP Encoder TXN & Tx DS245PP2 ...
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... EMPH and AUDIO is not visible Serial Input & Output Format IF1&OF1 Serial Input & Output Format IF2&OF2 Serial Input & Output Format IF3&OF3 Serial Input & Output Format IF2&OF4 TCBL is an input TCBL is an output Table 10. Hardware Mode 3 Start-up Options CS8420 Function 57 ...
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... OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso). 58 CS8420 DS245PP2 ...
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... AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times ...
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... The following pages contain the detailed pin de- scriptions for hardware mode 4. VD+ VD+ OSCLK H/S DFC1 SDOUT OLRCK Serial Audio Output C & U bit Data Buffer RERR PRO/C COPY ORIG EMPH/U AUDIO/V TCBL ISCLK ILRCK SDIN Serial APMS Audio Input AES3 TXP Encoder TXN & Tx CS8420 DS245PP2 ...
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... EMPH and AUDIO is not visible Serial Input & Output Format IF1&OF1 Serial Input & Output Format IF2&OF2 Serial Input & Output Format IF3&OF3 Serial Input & Output Format IF1&OF5 TCBL is an input TCBL is an output Table 11. Hardware Mode 4 Start-up Options CS8420 Function 61 ...
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... OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi). 62 CS8420 DS245PP2 ...
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... AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times ...
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... Table 12. Hardware Mode 5 Start-up Options VD+ VD+ DFC1 S/AES H/S C & U bit Data Buffer NVERR CHS COPY ORIG EMPH PRO AUDIO CS8420 Function - - Serial Output Port is Slave - - Serial Output Port is Master LO LO Serial Output Format OF1 LO HI Serial Output Format OF2 ...
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... AES3/SPDIF Receiver Interface: RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will frequency of 256x the input sample rate (Fsi). DS245PP2 CS8420 65 ...
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... Channel A is selected when CHS is low, channel B is selected when CHS is high User Data Output The U pin outputs user data from the AES3 receiver, clocked by rising and falling edges of OLRCK Channel Status Data Output The C pin outputs channel status data from the AES3 receiver, clocked by rising and falling edges of OLRCK. 66 CS8420 DS245PP2 ...
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... The following pages contain the detailed pin de- scriptions for hardware mode 6. VD+ VD+ VD+ S/AES H/S FILT DFC1 Data Buffer SFMT1 SFMT0 COPY/C ORIG EMPH AUDIO TCBL CS8420 Function 0 PRO=0, COPY=0, L=0 1 PRO=0, COPY=0, L=1 0 PRO=0, COPY=1, L=0 1 PRO=1 Function Serial Input Format IF1 ...
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... APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to set the port as a slave. AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. 68 COPY/C ...
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... The CEN pin determines how the channel status data bits are input. When CEN is low, hardware mode 6A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected channel status data. When CEN is high, hardware mode 6B is selected, where the COPY/C pin is used to enter serial channel status data. DS245PP2 CS8420 69 ...
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... AES3 transmitter and re- ceiver to cables and fiber-optic components. 15.1 AES3 Transmitter External Components The output drivers on the CS8420 are designed to drive both the professional and consumer interfac- es. The AES3 specification for professional/broad- cast use calls for a 110 source impedance and a balanced drive capability ...
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... Coax The circuit shown in Figure 38 may be used when CS8420 0.01 F external RS422 receivers, optical receivers or other RXP TTL/CMOS logic outputs drive the CS8420 receiv- 0. section. RXN TTL/CMOS 15.3 Isolating Transformer Requirements The transformer should be capable of operating from 1 MHz, which is equivalent to an au- dio data rate of 25 kHz to 108 kHz after bi-phase mark encoding ...
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... Manually accessing the E buffer The user can monitor the data being transferred by reading the E buffer, which is mapped into the reg- ister space of the CS8420, via the control port. The user can modify the data to be transmitted by writ- ing to the E buffer. ...
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... transfer. If the channel status block to transmit indicates PRO mode, then the CRCC byte is automatically calculated by the CS8420, and does not have to be written into the last byte of the block by the host microcontroller interrupt occurs Return Figure 42 ...
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... In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS8420 to out- put two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data ...
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... AES3 User (U) Bit Management The CS8420 U bit manager has four operating modes: Mode 1. Transmit all zeros. Mode 2. Block mode. Mode 3. Reserved Mode 4. IEC Consumer B. 16.2.1 Mode 1: Transmit All Zeros Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents or U data embedded in an input AES3 data stream ...
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... Example 1: Fsi/Fso = 2, N=4, IF=1: minimum proper padding is 53 bits. Example 2: Fsi/Fso = 1, N=4, IF=7: min proper padding is 9 bits. The CS8420 detects when an overwrite has oc- curred in the FIFO, and synchronously resets the entire FIFO structure to prevent corrupted U data from being merged into the transmitted AES3 data stream ...
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... AES3 Transmitter Output Jitter With a jitter free OMCK clock, what is the jitter added by the AES3 transmitter. Gain Error The difference in amplitude between the output and the input signal level, within the passband of the digital filter in the SRC. DS245PP2 CS8420 77 ...
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... MAX 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.013 0.697 0.713 17.70 0.291 0.299 0.040 0.060 0.394 0.419 10.00 0.016 0.050 0° 8° CS8420 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 18.10 7.40 7.60 1.02 1.52 10.65 ...
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Notes • ...
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