CS8420-CS Cirrus Logic Inc, CS8420-CS Datasheet - Page 22

• Manufacturer Part Number: CS8420-CS
• Description: Transceiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8420-CS

• Audio Control Type: Sample Rate Converter
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -10°C To +70°C
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Msl: MSL 2 - 1 Year
• Frequency Max: 108GHz
• Bandwidth: 20kHz
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

the channel status decodes are from the A channel
(CHS = 0) or B channel (CHS = 1).
The PRO (professional) bit is extracted directly.
Also, for consumer data, the COPY (copyright) bit
is extracted, and the category code and L bits are
decoded to determine SCMS status, indicated by
the ORIG (original) bit. Finally, the AUDIO bit is
extracted, and used to set an AUDIO indicator, as
described in the Non-Audio Auto Detection section
below.
If 50/15 µs pre-emphasis is detected, then this is re-
flected in the state of the EMPH pin.
The encoded sample word length channel status
bits are decoded according to AES3-1992 or IEC
60958. If the AES3 receiver is the data source for
the SRC, then the SRC audio input data is truncated
according to the channel status word length set-
tings. Audio data routed to the serial audio output
port is unaffected by the word length settings; all
24 bits are passed on as received.
The Appendix: Channel Status and User Data Buff-
er Management (page 72) describes the overall
handling of CS and U data.
22
RCBL
out
VLRCK
C, U
Output
RCBL and C output are only available in hardware mode 5.
RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames.
VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CU timing.
VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
If no SRC is used, and the serial audio output port is in master mode, VLRCK = OLRCK.
If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.
C, U transitions are aligned within 1% of VLRCK period to VLRCK edges
Figure 21. AES3 Receiver Timing for C & U pin output data
9.3
The incoming user data is buffered in a user acces-
sible buffer. Various automatic modes of re-trans-
mitting received U data are provided. The
Appendix: Channel Status and User Data Buffer
Management (page 72) describes the overall han-
dling of CS and U data.
Received U data may also be output to the U pin,
under the control of a control register bit. Depend-
ing on the data flow and clocking options selected,
there may not be a clock available to qualify the U
data output. Figure 21 illustrates the timing.
If the incoming user data bits have been encoded as
Q-channel subcode, then the data is decoded and
presented in 10 consecutive register locations. An
interrupt may be enabled to indicate the decoding
of a new Q-channel block, which may be read via
the control port.
9.4
Since it is possible to convey non-audio data in an
AES3 data stream, it is important to know whether
the incoming AES3 data stream is digital audio or
not. This information is typically conveyed in
channel status bit 1 (AUDIO), which is extracted
User Data Handling
Non-Audio Auto Detection
CS8420
DS245PP2