DS1337 Maxim, DS1337 Datasheet - Page 3

• Manufacturer Part Number: DS1337
• Description: The DS1337 serial real-time clock is a low-power clock/calendar with two programmable time-of-day alarms and a programmable square-wave output
• Manufacturer: Maxim

AC ELECTRICAL CHARACTERISTICS
(V
SCL Clock Frequency
Bus Free Time Between a
STOP and START Condition
Hold Time (Repeated)
START Condition (Note 10)
LOW Period of SCL Clock
HIGH Period of SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
(Notes 11, 12)
Data Setup Time (Note 13)
Rise Time of Both SDA and
SCL Signals (Note 14)
Fall Time of Both SDA and
SCL Signals (Note 14)
Setup Time for STOP
Condition
Capacitive Load for Each Bus
Line
I/O Capacitance (SDA, SCL)
Oscillator Stop Flag (OSF)
Delay
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
CC
= 1.8V to 5.5V, T
PARAMETER
Limits at -40°C are guaranteed by design and are not production tested.
SCL only.
SDA, INTA, and SQW/INTB.
I
Specified with the I
SQW enabled.
Specified with the SQW function disabled by setting INTCN = 1.
Using recommended crystal on X1 and X2.
The device is fully accessible when 1.8  V
After this period, the first clock pulse is generated
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
bridge the undefined region of the falling edge of SCL.
The maximum t
A fast-mode device can be used in a standard-mode system, but the requirement t
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t
line is released.
C
Guaranteed by design. Not production tested.
CCA
B
—total capacitance of one bus line in pF.
—SCL clocking at max frequency = 400kHz, V
A
= -40°C to +85°C.) (Note 1)
HD:DAT
2
C bus inactive, V
need only be met if the device does not stretch the LOW period (t
SYMBOL
t
t
t
t
t
HD:STA
SU:STA
HD:DAT
SU:DAT
SU:STO
t
t
C
t
f
t
HIGH
LOW
C
BUF
OSF
SCL
t
t
R
F
I/O
B
IL
= 0.0V, V
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
(Note 14)
(Note 15)
CC
CONDITIONS
 5.5V. Time and date are maintained when 1.3V  V
IH
IL
= V
3 of 16
= 0.0V, V
CC.
IH
= V
CC.
20 + 0.1C
20 + 0.1C
20 + 0.1C
20 + 0.1C
MIN
100
100
250
R max
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.0
0
0
0
+ t
SU:DAT
B
B
B
B
SU:DAT
DS1337 I
= 1000 + 250 = 1250ns before the SCL
LOW
 to 250ns must then be met. This is
TYP
100
) of the SCL signal.
2
C Serial Real-Time Clock
IHMIN
CC
 1.8V.
of the SCL signal) to
MAX
1000
400
100
300
300
300
400
0.9
10
UNITS
kHz
ms
pF
pF
s
s
s
s
s
s
ns
ns
ns
s