TMP86xy09NG Toshiba, TMP86xy09NG Datasheet - Page 43

• Manufacturer Part Number: TMP86xy09NG
• Manufacturer: Toshiba

Specifications of TMP86xy09NG

• Package: SDIP32
• Rom Types (m=mask,p=otp,f=flash): M/F
• Rom Size: 8/16
• Ram Size: 256/512
• Driver Led: 8
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 6
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: √
• Dual Clock: √
• Clock Gear: -
• Number Of I/o Ports: 26
• Power Supply (v): 2.7 to 5.5

3. Interrupt Control Circuit
3.1 Interrupt latches (IL15 to IL2)
Internal/External
Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are
maskable.
The interrupt latch is set to “1” by the generation of its interrupt request which requests the CPU to accept its inter-
rupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable
flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is domi-
nated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts.
fined instruction interrupt. When interrupt request is generated, the latch is set to “1”, and the CPU is requested to
accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting inter-
rupt. All interrupt latches are initialized to “0” during reset.
vidually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt
latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions
such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if inter-
rupt is requested while such instructions are executed.
The TMP86C809NG has a total of 17 interrupt sources excluding reset, of which 1 source levels are multiplexed.
Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors.
Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Inter-
Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1<ATOUT> to “0” (It is set for the “reset request” after reset is
Note 3: To use the watchdog timer interrupt (INTWDT), clear WDTCR1<WDTOUT> to "0" (It is set for the "Reset request" after
An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the unde-
The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" indi-
Interrupt latches are not set to “1” by an instruction.
Since interrupt latches can be read, the status for interrupt requests can be monitored by software.
External
External
External
External
External
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
rupt Source Selector (INTSEL)).
cancelled). For details, see “Address Trap”.
reset is released). For details, see "Watchdog Timer".
(Reset)
INTSWI (Software interrupt)
INTUNDEF (Executed the undefined instruction
interrupt)
INTATRAP (Address trap interrupt)
INTWDT (Watchdog timer interrupt)
INT0
INT1
INTTBT
INTTC1
INTRXD
INTTXD
INTTC3
INTTC4
INT3
INTADC
INTSEI
INT4
INT5
Interrupt Factors
Page 33
Non-maskable
Non-maskable
Non-maskable
Non-maskable
Non-maskable
IMF• EF4 = 1, INT0EN = 1
IMF• EF5 = 1
IMF• EF6 = 1
IMF• EF7 = 1
IMF• EF8 = 1
IMF• EF9 = 1
IMF• EF10 = 1
IMF• EF11 = 1, IL11ER = 0
IMF• EF11 = 1, IL11ER = 1
IMF• EF12 = 1
IMF• EF13 = 1
IMF• EF14 = 1
IMF• EF15 = 1
Enable Condition
Interrupt
Latch
IL10
IL12
IL13
IL14
IL15
IL11
IL2
IL3
IL4
IL5
IL6
IL7
IL8
IL9
–
–
–
TMP86C809NG
Address
Vector
FFFE
FFFC
FFFC
FFEE
FFEC
FFEA
FFFA
FFF8
FFF6
FFF4
FFF2
FFF0
FFE8
FFE6
FFE4
FFE2
FFE0
Priority
10
12
13
14
15
16
11
2
2
2
2
5
6
7
8
9
1