74LVTH125MTC Fairchild Semiconductor, 74LVTH125MTC Datasheet - Page 8

• Manufacturer Part Number: 74LVTH125MTC
• Description: IC BUFF TRI-ST QD LOW V 14TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74LVTHr

Specifications of 74LVTH125MTC

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 4
• Number Of Bits Per Element: 1
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Logic Family: 74LVT
• Number Of Channels Per Chip: Quad
• Polarity: Non-Inverting
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 32 mA
• Low Level Output Current: 64 mA
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 3
• Output Type: 3-State
• Propagation Delay Time: 4.9 ns @ 2.7 V or 3.9 ns @ 3.3 V
• Logic Device Type: Buffer, Non Inverting
• Supply Voltage Range: 2.7V To 3.6V
• Logic Case Style: TSSOP
• No. Of Pins: 14
• Operating Temperature Range: -40°C To +85°C
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Family Type: LVTH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1998 Fairchild Semiconductor Corporation
74LVTH125 Rev. 1.4.0
Physical Dimensions
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
A. CONFORMS TO JEDEC REGISTRATION MO-153,
B. DIMENSIONS ARE IN MILLIMETERS
E. LANDPATTERN STANDARD: SOP65P640X110-14M
D. DIMENSIONING AND TOLERANCES PER ANSI
F. DRAWING FILE NAME: MTC14REV6
AND TIE BAR EXTRUSIONS
VARIATION AB, REF NOTE 6
Y14.5M, 1982
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
0.43 TYP
(Continued)
8
0.65
R0.09 min
0.45
1.65
1.00
R0.09min
12.00°
TOP & BOTTOM
6.10
www.fairchildsemi.com