74HCT126D,652 NXP Semiconductors, 74HCT126D,652 Datasheet - Page 2

• Manufacturer Part Number: 74HCT126D,652
• Description: IC BUFFER DVR TRI-ST QD 14SOICN
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT126D,652

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 4
• Number Of Bits Per Element: 1
• Current - Output High, Low: 2mA, 2mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Logic Family: HCT
• Number Of Channels Per Chip: 4
• Polarity: Non-Inverting
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 6 mA
• Low Level Output Current: 6 mA
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 4 / 4
• Output Type: 3-State
• Propagation Delay Time: 24 ns at 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Details
• Other names: 74HCT126D; 74HCT126D; 933757050652

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT126 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The HC/HCT126 are four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by
the output enable input (nOE). A LOW at nOE causes the outputs to assume a HIGH impedance OFF-state.
The “126” is identical to the “125” but has active HIGH enable inputs.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
December 1990
t
C
C
PHL
Output capability: bus driver
I
Quad buffer/line driver; 3-state
I
PD
SYMBOL
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
2
propagation delay nA to nY
input capacitance
power dissipation capacitance per buffer
= 25 C; t
V
f
o
CC
) = sum of outputs
2
f
r
i
= t
+
I
PARAMETER
= GND to V
I
f
= GND to V
= 6 ns
(C
L
V
CC
CC
2
CC
f
o
) where:
1.5 V
2
.
C
notes 1 and 2
L
D
= 15 pF; V
in W):
CONDITIONS
CC
= 5 V
9
3.5
23
HC
TYPICAL
74HC/HCT126
Product specification
11
3.5
24
HCT
ns
pF
pF
UNIT