M25PX32 Numonyx, B.V., M25PX32 Datasheet
M25PX32
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M25PX32 Summary of contents
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... More than 100 000 write cycles per sector More than 20 year data retention Packages – ECOPACK® (RoHS compliant) January 2008 32-Mbit, dual I/O, 4-Kbyte subsector erase, Rev 6 M25PX32 VFQFPN8 (MP) 6 × SO8W (MW) 208 mils SO16 (MF) 300 mils 1/65 www ...
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... Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13 4.5 Fast Bulk Erase mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 14 4.7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.8.1 4.8.2 4.9 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 2/65 Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Specific hardware and software protection . . . . . . . . . . . . . . . . . . . . . . 16 M25PX32 ) . . . . . . . . . . . . 10 PP ...
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... M25PX32 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.5 Write Status Register (WRSR 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at higher speed (FAST_READ 6.8 Dual Output Fast Read (DOFR 6.9 Read Lock Register (RDLR 6.10 Read OTP (ROTP 6.11 Page Program (PP 6.12 Dual Input Fast Program (DIFP ...
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... VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 19. SO8W 8-lead plastic small outline, 208 mils body width, package mechanical data Table 20. SO16 wide - 16-lead plastic small outline, 300 mils body width, mechanical data . . . . . . . 62 Table 21. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 22. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4/65 M25PX32 ...
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... M25PX32 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. VFQFPN and SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Bus Master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 9. ...
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... Description 1 Description The M25PX32 Mbit ( serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The M25PX32 supports two new, high-performance dual input/output instructions: Dual Output Fast Read (DOFR) instruction used to read data MHz by using ...
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... C M25PX32 S W/V PP HOLD V SS Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect/Enhanced Program supply voltage Hold Supply voltage Ground M25PX32 DQ1 section for package dimensions, and how to identify pin-1. Description DQ1 ...
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... Description Figure 3. SO16 connections Don’t use. 2. See Package mechanical 8/65 M25PX32 HOLD DQ1 8 9 section for package dimensions, and how to identify pin-1. M25PX32 C DQ0 W/V PP AI13721b ...
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... M25PX32 2 Signal descriptions 2.1 Serial Data output (DQ1) This output signal is used to transfer data serially out of the device. Data are shifted out on the falling edge of Serial Clock (C). During the Dual Input Fast Program (DIFP) instruction, pin DQ1 is used as an input latched on the rising edge of the Serial Clock (C). ...
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... the supply voltage. CC 2.8 V ground the reference for the V SS 10/65 Table 9). (as defined in Table 14) it acts as an additional power supply PPH must be stable until the Bulk Erase algorithm is PP supply voltage. CC M25PX32 ) PP ) the pin is seen as a control CC ...
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... Serial Data output (DQ1) line at a time, the other devices are high impedance. Resistors R (represented in that the M25PX32 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance ...
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... R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA DQ0 DQ1 12/ µs <=> the application must ensure that the Bus p MSB M25PX32 MSB AI13730 ...
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... M25PX32 4 Operating features 4.1 Page programming To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory ...
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... V PP must be 25 °C ±10 ° Deep Power-down (DP)), this can be used as an extra software protection Section 6.4: Read Status Register (RDSR) (see Table 13) PPH should be less than 80 hours. PPH . The CC2 M25PX32 PPH . CC1 for a ...
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... The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25PX32 features the following data protection mechanisms: Power On Reset and an internal timer (t changes while the power supply is outside the operating specification ...
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... Sector protected from Program/Erase/Write operations, protection status reversible Sector unprotected from Program/Erase/Write operations, Sector protection status cannot be changed except by a power-up. Sector protected from Program/Erase/Write operations, Sector protection status cannot be changed except by a Power-up. bits) and the Top/Bottom bit (see M25PX32 Table 9: Lock Register out. Section 6.4.4: TB bit) to ...
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... M25PX32 Table 3. Protected area sizes Status Register contents bit bit 2 bit The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are ...
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... To restart communication with the device necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents the device from going back to the Hold condition. Figure 6. Hold condition activation C HOLD 18/65 Figure 6). Hold Condition (standard use) M25PX32 Figure 6). Hold Condition (non-standard use) AI02029D ...
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... M25PX32 5 Memory organization The memory is organized as: 4 194 304 bytes (8 bits each) 1024 subsectors (4 Kbytes each) 64 sectors (64 Kbytes each) 16384 pages (256 bytes each) 64 OTP bytes located outside the main memory array Each page can be individually programmed (bits are programmed from 1 to 0). The device is Subsector, Sector or Bulk Erasable (bits are erased from but not Page Erasable ...
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... M25PX32 Subsector Address range 847 34F000h 34FFFFh 832 340000h 340FFFh 831 33F000h 33FFFFh 816 330000h 330FFFh 815 32F000h 32FFFFh 800 320000h 320FFFh 799 ...
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... M25PX32 Table 4. Memory organization (continued) Sector Subsector 671 41 656 655 40 640 639 39 624 623 38 608 607 37 592 591 36 576 575 35 560 559 34 544 543 33 528 527 32 512 511 31 496 Address range Sector 29F000h 29FFFFh 30 290000h 290FFFh 28F000h 28FFFFh 29 280000h 280FFFh 27F000h ...
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... DFFFFh 2 D0000h D0FFFh CF000h CFFFFh 1 C0000h C0FFFh BF000h BFFFFh B0000h B0FFFh AF000h AFFFFh 0 A0000h A0FFFh 9F000h 9FFFFh 90000h 90FFFh M25PX32 Subsector Address range 143 8F000h 8FFFFh 128 80000h 80FFFh 127 7F000h 7FFFFh 112 70000h 70FFFh 111 6F000h 6FFFFh 96 60000h 60FFFh 95 5F000h ...
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... M25PX32 6 Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data input(s) DQ0 (DQ1) is (are) sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data input(s) DQ0 (DQ1), each bit being latched on the rising edges of Serial Clock (C) ...
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... M25PX32 Address Dummy Data bytes bytes bytes 06h 04h ...
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... M25PX32 6.1 Write Enable (WREN) The Write Enable (WREN) instruction The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Dual Input Fast Program (DIFP), Program OTP (POTP), Write to Lock Register (WRLR), Subsector Erase (SSE), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction ...
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... Program OTP (POTP) instruction completion Subsector Erase (SSE) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Figure 9. Write Disable (WRDI) instruction sequence 26/65 (Figure 9) resets the Write Enable Latch (WEL) bit Instruction DQ0 High Impedance DQ1 AI13732 M25PX32 ...
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... M25PX32 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows to read the device identification data: Manufacturer identification (1 byte) Device identification (2 bytes) A Unique ID code (UID) (17 bytes, of which 16 available upon customer request). The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. ...
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... Instructions Figure 10. Read Identification (RDID) instruction sequence and data-out sequence 28/65 M25PX32 ...
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... M25PX32 6.4 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... DQ0 High Impedance DQ1 30/65 Table 3: Protected area Instruction Status Register Out MSB Table 3: Protected area sizes) sizes driven Low Status Register Out MSB M25PX32 0 7 AI13734 ...
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... M25PX32 6.5 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL) ...
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... Protected area Unprotected area Protected against Ready to accept Page Program, Page Program and Sector Erase and Sector Erase Bulk Erase instructions Protected against Ready to accept Page Program, Page Program and Sector Erase and Sector Erase Bulk Erase instructions Table M25PX32 (1) ...
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... M25PX32 6.6 Read Data Bytes (READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that ...
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... Instruction 24-bit address High Impedance Dummy byte DATA OUT MSB DATA OUT MSB M25PX32 0 7 MSB AI13737 ...
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... M25PX32 6.8 Dual Output Fast Read (DOFR) The Dual Output Fast Read (DOFR) instruction is very similar to the Read Data Bytes at higher speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin DQ0 and pin DQ1) instead of only one. Outputting the data on two pins instead of one doubles the data transfer bandwidth compared to the Read Data Bytes at higher speed (FAST_READ) instruction ...
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... Section 7: Power-up and Instruction 24-bit address MSB High Impedance , during the falling edge of C Function power-down Lock Register Out MSB M25PX32 39 0 AI13738 ...
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... M25PX32 6.10 Read OTP (ROTP) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read OTP (ROTP) instruction is followed by a 3-byte address (A23- A0) and a dummy byte. Each bit is latched in on the rising edge of Serial Clock (C). Then the memory contents at that address are shifted out on Serial Data output (DQ1). ...
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... Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see 38/65 Figure 18. Table 3 and Table 4) is not executed. M25PX32 Table 17: AC ...
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... M25PX32 Figure 18. Page Program (PP) instruction sequence DQ0 Data byte DQ0 MSB 1. Address bits A23 to A22 are Don’t care Instruction 24-bit address MSB Data byte 3 ...
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... At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the Block Protect (BP2, BP1, BP0) bits (see 40/65 Figure 19. Table 2 and Table 3) is not executed. M25PX32 ...
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... M25PX32 Figure 19. Dual Input Fast Program (DIFP) instruction sequence DQ0 DQ1 DQ0 DATA DQ1 MSB 1. A23 to A22 are Don't care Instruction 24-bit address High Impedance ...
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... Therefore, as soon as bit 0 of byte 64 (control byte) is set to ‘0’, the 64 bytes of the OTP memory array become read-only in a permanent way. Any Program OTP (POTP) instruction issued while an Erase, Program or Write cycle is in progress is rejected without having any effect on the cycle that is in progress. 42/65 Figure 20. Figure 21) is used to permanently lock the M25PX32 ...
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... M25PX32 Figure 20. Program OTP (POTP) instruction sequence DQ0 DQ0 MSB 1. A23 to A7 are Don't care ≤ n ≤ 65 Figure 21. How to permanently lock the 64 OTP bytes Byte Byte Byte Instruction 24-bit address ...
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... MSB (1) Bit b7-b2 b1 Sector Lock Down bit value (refer to b0 Sector Write Lock bit value (refer to Section 7: Power-up and minimum value. SHSL Lock Register MSB Value ‘0’ Table 9) Table 9) power-down. M25PX32 AI13740 ...
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... M25PX32 6.15 Subsector Erase (SSE) The Subsector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL) ...
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... DQ1 1. Address bits A23 to A22 are Don’t care. 46/ valid address for the Sector Erase (SE) instruction. Chip Select Figure 24. Table 3 and Table 4) is not executed Instruction 23 22 MSB M25PX32 ) Bit Address AI13742 ...
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... M25PX32 6.17 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 26. Deep Power-down (DP) instruction sequence S C DQ0 48/65 Table 16). Figure 26 Instruction M25PX32 before the supply current is reduced Standby mode Deep Power-down mode to CC1 AI13744 ...
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... M25PX32 6.19 Release from Deep Power-down (RDP) Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down (RDP) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data input (DQ0) ...
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... WI is stable and in the V CC VSL modes. – all operations are disabled, and WI rises above the V CC (min), the device can be selected for CC CC min to V max voltage CC CC M25PX32 is less supply. ...
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... M25PX32 Figure 28. Power-up timing (max (min) Reset state of the device V WI Table 11. Power-up timing and V Symbol ( (min low VSL CC (1) t Time delay to write instruction PUW (1) V Write Inhibit voltage WI 1. These parameters are characterized only. Program, Erase and Write commands are rejected by the device ...
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... Compliant with JEDEC Std J-STD-020C (for small body, Sn- assembly), the ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1 = 100 pF 1500 Ω 500 Ω). 52/65 Table 12: Absolute maximum ratings Parameter (2) M25PX32 may Min Max Unit –65 150 °C ...
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... M25PX32 10 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters ...
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... PPH , PPH – 0.5 0. –0.2 CC M25PX32 Unit ± 2 µA ± 2 µA 50 µA 10 µ +0 ...
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... M25PX32 Table 17. AC characteristics Symbol Alt ( CLH ( CLL (4) t CLCH (4) t CHCL t t SLCH CSS t CHSL t t DVCH DSU t t CHDX DH t CHSH t SHCH t t SHSL CSH ( SHQZ DIS t t CLQV CLQX ...
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... Bulk Erase cycle time Bulk Erase cycle time ( PPH = 25° tSLCH tCHDX MSB IN High Impedance Table 13 and Table 14 (2) Min Typ 1.3 0.8 (9) int(n/8) × 0.025 0 tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN M25PX32 Max Unit 150 AI13728 ...
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... M25PX32 Figure 31. Write Protect Setup and Hold timing during WRSR when SRWD=1 W/V PP tWHSL S C DQ0 DQ1 Figure 32. Hold timing S C DQ1 DQ0 HOLD High Impedance tHLCH tCHHL tCHHH tHLQZ DC and AC parameters tSHWL AI07439c tHHCH tHHQX AI13746 57/65 ...
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... DC and AC parameters Figure 33. Output timing S C tCLQV tCLQX DQ1 ADDR. DQ0 LSB IN Figure 34. V PPH S C DQ0 V PPH V PP 58/65 tCLQV tCLQX timing BE tVPPHSL M25PX32 tCH tCL LSB OUT tQLQH tQHQL End of BE (identified by WIP polling) tSHQZ AI13729 ai13726 ...
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... M25PX32 11 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... Typ Min Max 0.85 0.80 1.00 0.00 0.05 0.65 0.20 0.40 0.35 0.48 6.00 5.75 3.40 3.20 3.60 5.00 4.75 4.00 3.80 4.30 1.27 – – 0.10 0.00 0.60 0.50 0.75 12° 0.15 0.10 0.05 M25PX32 Inches Typ Min Max 0.0335 0.0315 0.0394 0.0000 0.0020 0.0256 0.0079 0.0157 0.0138 0.0189 0.2362 0.2264 0.1339 0.1260 0.1417 0.1969 0.1870 0.1575 0.1496 0.1693 0.0500 – – 0.0039 0.0000 0.0236 0.0197 0.0295 12° 0.0059 ...
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... M25PX32 Figure 36. SO8W 8-lead plastic small outline, 208 mils body width, package outline 1. Drawing is not to scale. Table 19. SO8W 8-lead plastic small outline, 208 mils body width, package mechanical data Symbol Millimeters ...
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... Millimeters Typ Min Max 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 10.10 10.50 7.40 7.60 1.27 – – 10.00 10.65 0.25 0.75 0.40 1.27 0° 8° 0. 45˚ ddd Inches Typ Min 0.093 0.004 0.013 0.009 0.398 0.291 0.050 – 0.394 0.010 0.016 0° M25PX32 Max 0.104 0.012 0.020 0.013 0.413 0.299 – 0.419 0.030 0.050 8° 0.004 ...
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... F = Tape and reel packing ECOPACK® (RoHS compliant) 1. Secure options are available upon customer request. Note: For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest Numonyx Sales Office. (1) Ordering information M25PX32 – 63/65 ...
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... Document status promoted from Preliminary Data to full Datasheet. Section 6.3: Read Identification (RDID) updated. 5 Modified the minimum value for t Minor text changes. 6 Applied Numonyx branding. M25PX32 Changes Section 4.8.2: Specific hardware Section 6.3: Read Identification ). CC2 Section 7: Power-up and power- Chapter 1: Description and added Table 21 ...
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... M25PX32 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...