MSC7116 Freescale Semiconductor / Motorola, MSC7116 Datasheet
MSC7116
Available stocks
Related parts for MSC7116
MSC7116 Summary of contents
Page 1
... DMA transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the OCE10. © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Document Number: MSC7116 MSC7116 MAP-BGA–400 17 mm × • Multi-channel DMA controller with 32 time-multiplexed ...
Page 2
... Package Information .58 6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 List of Figures Figure 1. MSC7116 Block Diagram Figure 2. MSC7116 Molded Array Process-Ball Grid Array (MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. MSC7116 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Timing Diagram for a Reset Configuration Write . . . . 25 Figure 5 ...
Page 3
... AMEC ASAPB 64 32 ASM1 64 ASIB 64 AMENT 32 to EMI Ethernet to DMA MAC MII/RMII Figure 1. MSC7116 Block Diagram MSC7116 Data Sheet, Rev 128 SRAM (192 KB) 64 Boot ROM 128 (8 KB) External Bus External Memory from 32 Interface Interrupts Interrupt Control Host HDI16 ...
Page 4
... Pin Assignments 1 Pin Assignments This section includes diagrams of the MSC7116 package ball grid array layouts and pinout allocation tables. 1.1 MAP-BGA Ball Layout Diagrams Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers. ...
Page 5
... DD V TDI CRS TX_EN RXD0 RXD2 W MDC RX_ER TXCLK TXD1 RXD3 Y RX_DV GND RXD1 TXD0 RXCLK Figure 3. MSC7116 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View Freescale Semiconductor Bottom View GND HD0 HD1 HD4 HD6 HD7 HD10 BM2 NC ...
Page 6
... Pin Assignments 1.2 Signal List By Ball Location Table 1 lists the signals sorted by ball number and configuration. Table 1. MSC7116 Signals by Ball Designator Number End of Reset GPI Enabled A10 A11 A12 A13 A14 A15 A16 BM3 A17 A18 A19 A20 ...
Page 7
... Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled B14 B15 BM2 B16 B17 B18 B19 B20 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 Freescale Semiconductor Signal Names ...
Page 8
... Pin Assignments Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 ...
Page 9
... Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 H1 Freescale Semiconductor ...
Page 10
... Pin Assignments Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 J10 J11 J12 J13 J14 J15 J16 J17 10 Signal Names ...
Page 11
... Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled J18 J19 J20 HDSP K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 L10 L11 L12 L13 Freescale Semiconductor Signal Names ...
Page 12
... Pin Assignments Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled L14 L15 L16 L17 L18 L19 L20 M10 M11 M12 M13 M14 M15 M16 M17 M18 GPIA14 M19 GPIA12 M20 GPIA13 ...
Page 13
... Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 GPIA15 N20 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 Freescale Semiconductor ...
Page 14
... Pin Assignments Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 ...
Page 15
... Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V10 V11 SWTE V12 GPIA8 V13 GPIA4 V14 GPIA0 V15 GPIA28 ...
Page 16
... Pin Assignments Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled V18 GPIA24 V19 V20 GPIA17 W10 BM0 W11 GPIA10 W12 GPIA7 W13 GPIA3 W14 GPIA1 W15 W16 GPIA27 W17 GPIA19 W18 GPIA23 W19 GPIA26 ...
Page 17
... Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled Y14 GPIA2 Y15 GPIA29 Y16 Y17 GPIA20 Y18 GPIA21 Y19 Y20 GPIA25 2 Electrical Characteristics This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC711x Reference Manual. ...
Page 18
... Electrical Characteristics Table 2 describes the maximum electrical ratings for the MSC7116. Rating Core supply voltage Memory supply voltage PLL supply voltage I/O supply voltage Input voltage Reference voltage Maximum operating temperature Minimum operating temperature Storage temperature range Notes: 1. Functional operating conditions are given in Table 3. ...
Page 19
... Thermal Characteristics Table 4 describes thermal characteristics of the MSC7116 for the MAP-BGA package. Table 4. Thermal Characteristics for MAP-BGA Package Characteristic 1, 2 Junction-to-ambient 1, 3 Junction-to-ambient, four-layer board 4 Junction-to-board 5 Junction-to-case 6 Junction-to-package-top Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance ...
Page 20
... V REF exceed ±2% of the DC value not applied directly to the MSC7116 device the level measured at the far end signal termination. It should be equal This rail should track variations in the DC level of V REF Output leakage for the memory interface is measured with all outputs disabled ≤ ...
Page 21
... You must ensure that maximum frequency values are not exceeded (see CLKO Table 6. Maximum Frequencies Table 7. Clock Frequencies in MHz Symbol Table 8. System Clock Parameters MSC7116 Data Sheet, Rev. 13 Electrical Characteristics Maximum in MHz 266 67 133 50 Min Max 10 100 CLKIN — ...
Page 22
... Electrical Characteristics 2.5.2 Configuring Clock Frequencies This section describes important requirements for configuring clock frequencies in the MSC7116 device when using the PLL block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL): • PLLDVF field. Specifies the PLL division factor (PLLDVF + 1) to divide the input clock frequency of the divider block is the input to the multiplier block. • ...
Page 23
... MHz Core limited to 2 × maximum DDR frequency 166 ≤ core clock ≤ 266 MHz Core limited to 2 × maximum DDR frequency MSC7116 Data Sheet, Rev. 13 Electrical Characteristics Maximum PLLMLTF Value 532/Divided Input Clock vco ...
Page 24
... Reset Timing The MSC7116 device has several inputs to the reset logic. All MSC7116 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 14 describes the reset sources. ...
Page 25
... Reset Configuration The MSC7116 has two mechanisms for writing the reset configuration: • From a host through the host interface (HDI16) 2 • From memory through the I Five signal levels (see Chapter 1 for signal description details) are sampled on operating conditions: • BM[0–1] • ...
Page 26
... D0 D1 201 201 Table 18. DDR DRAM Output AC Timing Symbol DDKHAS t DDKHAX t DDKHCS t DDKHCX t DDKHMH MSC7116 Data Sheet, Rev. 13 Min Max — V – 0.31 REF 0.3 REF DDM — 900 — 900 Min Max 10 — 6.67 — 0.5 × t – ...
Page 27
... DDKLDS 3 t DDKHDX, t DDKLDX t DDKHMP t DDKHME 200 205 207 NOOP 211 208 209 209 D0 D1 210 210 MSC7116 Data Sheet, Rev. 13 Electrical Characteristics Min Max 0.25 × t – 750 — CK 0.25 × t – 750 — CK –0.25 × t — CK –600 600 212 Unit ...
Page 28
... R Figure 7. DDR DRAM AC Test Load Symbol Table 20. TDM Timing Expression TC 0.4 × TC 0.4 × TC 300 301 304 303 305 303 310 Figure 8. TDM Receive Signals MSC7116 Data Sheet, Rev OUT = 50 Ω L DDR DRAM V ± 0.31 V REF 0.5 × V DDM Min Max 20.0 — 8.0 — ...
Page 29
... Figure 9. TDM Transmit Signals Table 21. Receive Signal Timing Characteristics 800 802 803 Valid Figure 10. Ethernet Receive Signal Timing MSC7116 Data Sheet, Rev. 13 Electrical Characteristics 302 309 308 311 Min Max 40 — 20 — — ...
Page 30
... RMII: CRS_DV minimum pulse width (1.5 x REFCLK period) CRS COL CRS_DV Figure 12. Asynchronous Input Signal Timing 30 Table 22. Transmit Signal Timing Characteristics 800 801 806 805 Figure 11. Ethernet Receive Signal Timing Characteristics MSC7116 Data Sheet, Rev. 13 Min Max Unit 40 — 20 — — 7 — ...
Page 31
... MDC rising edge to MDIO input hold time MDC (output) MDIO (output) MDIO (input) Figure 13. Serial Management Channel Timing Freescale Semiconductor Characteristics 808 809 811 813 814 MSC7116 Data Sheet, Rev. 13 Electrical Characteristics Min Max 400 — 160 — 160 — 0 — ...
Page 32
... Data Register” 5,8,10 = 3.333 ns. CORE = 30 pF for maximum delay timings and C L MSC7116 Data Sheet, Rev Expression Value T Note 1 CORE 2.0 × 9.0 Note 11 CORE 1.5 × T Note 11 CORE 2.5 × T Note 11 CORE 1.5 × T Note 11 CORE 2.5 × T ...
Page 33
... HRD HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 15. Read Timing Diagram, Double Data Strobe Freescale Semiconductor HRW 44a HDS 44a MSC7116 Data Sheet, Rev 44b 44c 44b 44a ...
Page 34
... Figure 16. Write Timing Diagram, Single Data Strobe HA[0–2] HCS[1–2] HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 17. Write Timing Diagram, Double Data Strobe HWR 47 MSC7116 Data Sheet, Rev Freescale Semiconductor ...
Page 35
... Figure 18. Host DMA Read Timing Diagram, HPCR[OAD HD[0–15] Figure 19. Host DMA Write Timing Diagram, HPCR[OAD Freescale Semiconductor HREQ (Output) 64 44a RX[0–3] HACK Read 50 49 Data HD[0–15] Valid (Output) HREQ (Output TX[0–3] Write HACK 47 Data Valid (Input) MSC7116 Data Sheet, Rev 44b ...
Page 36
... A 452 C K Data Byte Data Byte 2 Figure 20 Timing Diagram MSC7116 Data Sheet, Rev. 13 Fast Max 400 — — — — BCK — — 700 300 — — Stop Condition Start Condition 457 459 460 ...
Page 37
... Figure 21. UART Input Timing 402 402 Figure 22. UART Output Timing Table 28. EE0 Timing Type Asynchronous Synchronous to core clock pin Figure 23. EE Pin Timing MSC7116 Data Sheet, Rev. 13 Min Max Unit — 133 MHz 7.52 — ns 120.3 — ns — — ...
Page 38
... Table 30. GPIO Signal Timing Type Asynchronous Synchronous to core clock Asynchronous Asynchronous pins. GPI/GPO 601 602 Figure 25. GPI/GPO Pin Timing MSC7116 Data Sheet, Rev. 13 Min 1.5 × APBCLK periods 1 APBCLK period Min 1.5 × APBCLK periods 1 APBCLK period 1.5 × APBCLK periods 3 × APBCLK periods 6 Freescale Semiconductor ...
Page 39
... All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface. TCK (Input) Figure 26. Test Clock Input Timing Diagram Freescale Semiconductor Table 31. JTAG Timing × 1 701 703 MSC7116 Data Sheet, Rev. 13 All frequencies Min Max 0.0 40.0 25.0 — 11.0 — 0.0 3.0 5.0 — 14.0 — 0.0 20.0 ...
Page 40
... Figure 28. Test Access Port Timing Diagram TRST (Input) 712 40 704 Input Data Valid 706 Output Data Valid 707 708 Input Data Valid 710 Output Data Valid 711 Figure 29. TRST Timing Diagram MSC7116 Data Sheet, Rev 705 V IH 709 Freescale Semiconductor ...
Page 41
... I/O The power dissipation values for the MSC7116 are listed in Table 4. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes ...
Page 42
... Core Memory Reference I/O You should supply the MSC7116 core voltage via a variable switching supply or regulator to allow for compatibility with possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across V and GND and the I/O section is supplied with 3.3 V (± 10%) across V the DDR memory controller block. The memory voltage is supplied with 2.5 V across V and must be between 0.49 × ...
Page 43
... Refer to Figure 30 for relative timing for power sequencing case 1. Ramp-up <10 ms <10 ms Freescale Semiconductor and V DDIO <10 ms Time Figure 30. Voltage Sequencing Case 1 MSC7116 Data Sheet, Rev. 13 Hardware Design Considerations is less than 10 ms. DDC and V is less than 10 ms for DDC DDM Ramp-down V = 3.3 V ...
Page 44
... Refer to Figure 31 for relative timing for Case 2. Ramp-up < (2.5 V) supplies simultaneously (second). DDM and V DDIO and V DDIO <10 ms Time Figure 31. Voltage Sequencing Case 2 MSC7116 Data Sheet, Rev less than 10 ms. DDC DDM is less than 10 ms. DDC and V is less than 10 ms for DDC DDM Ramp-down ...
Page 45
... V) supplies simultaneously (third). REF and V DDIO (1.25 V) supplies simultaneously (first). REF and V DDIO <10 ms Time Figure 32. Voltage Sequencing Case 3 MSC7116 Data Sheet, Rev. 13 Hardware Design Considerations is less than 10 ms. DDC is less than 10 ms. DDC and V is less than 10 ms for DDC DDM Ramp-down ...
Page 46
... V), and V (1.25 V) supplies simultaneously (second). DDM REF and V DDIO (1.25 V), and V (2.5 V) supplies simultaneously (first). REF DDM Time Figure 33. Voltage Sequencing Case 4 MSC7116 Data Sheet, Rev less than 10 ms. DDC and V is less than 10 ms for DDC DDM Ramp-down V = 3.3 V DDIO ...
Page 47
... Verify risks related to current spikes using actual information for the specific application. Freescale Semiconductor and V DDIO and V DDIO <2 ms Time Figure 34. Voltage Sequencing Case 5 MSC7116 Data Sheet, Rev. 13 Hardware Design Considerations is less than 10 ms. DDM is less than 10 ms. DDM and V is less than 2 ms for DDC ...
Page 48
... The second decoupling level should consist of two bulk/tantalum decoupling capacitors, one 10 μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7116 voltage pins. Additionally, the maximum drop between the power supply and the DSP device should ...
Page 49
... P CORE PERIPHERALS DDRIO C × × F × 10 – 750 pF × (1 × 266 MHz × 10 –3 MSC7116 Data Sheet, Rev. 13 Hardware Design Considerations Current Rating 1.2 V 1.5 A per device 2.5 V 0.5 A per device 10 µA per device 3.3 V 1.0 A per device + P IO LEAKAGE = 287 mW Eqn ...
Page 50
... Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage, termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7116 device, the 2.5 V power source provides the power for the termination, which is a static value per signal driven high. ...
Page 51
... Either a smaller value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7116 output current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design). ...
Page 52
... After the boot program is loaded, it can enable the PLL and start the device operating at a higher speed. The MSC7116 can boot from an external host through the HDI16 or download a user program through the I boot operating mode is set by configuring the See the MSC711x Reference Manual for details of boot program operation ...
Page 53
... Then the MSC7116 device initiates accesses to the SPI module, downloading data to the MSC7116 device. When the SPI routines run in the boot ROM, the MSC7116 is always configured as the SPI master. Booting through the SPI is supported for serial EEPROM devices and serial Flash devices. When a READ_ID instruction is issued to the serial memory device and the device returns a value of 0x00 or 0xFF, the routines for accessing a serial EEPROM are used maximum frequency of 4 Mbps ...
Page 54
... Hardware Design Considerations 3.5 DDR Memory System Guidelines MSC7116 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown in Figure 36. Technique B is the most popular termination technique. ...
Page 55
... Figure 37. SSTL Power Value as a high current power source. This section outlines TT DC offsets. Although they are isolated supplies, one possible solution is to use a REF as follows: REF island and ensure a good, solid connection. TT MSC7116 Data Sheet, Rev. 13 Hardware Design Considerations Receiver V REF 55 ...
Page 56
... If stack-up allows, keep DDR data groups away from the address and control nets. — Route address and control on separate critical layers. — If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages. 56 DQS + the same layer. Avoid switching layers within a byte group. MSC7116 Data Sheet, Rev. 13 Freescale Semiconductor ...
Page 57
... Connectivity Guidelines This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7116 device. Following are guidelines for signal groups and configuration settings: • Clock and reset signals. — is used to configure the MSC7116 device and is sampled on the deassertion of ...
Page 58
... MSC711x Reference Manual (MSC711xRM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. • Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC7116 device. • SC140/SC1400 DSP Core Reference Manual. Covers the SC140 and SC1400 core architecture, control registers, clock registers, program control, and instruction set ...
Page 59
... Change the PLL filter resistor from 20 Ω Ω in Section 3.2.5. 13 Apr 2008 Freescale Semiconductor Table 36. Document Revision History Description 2 C timing specifications interface. and V CCSYN CCSYN1 2 C boot information and added SPI boot information. MSC7116 Data Sheet, Rev. 13 Revision History . 59 ...
Page 60
... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MSC7116 Rev. 13 4/2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...