MSC7118 Freescale Semiconductor / Motorola, MSC7118 Datasheet

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MSC7118

Manufacturer Part Number
MSC7118
Description
Low-Cost 16-bit DSP with DDR Controller
Manufacturer
Freescale Semiconductor / Motorola
Datasheet

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Freescale Semiconductor
Data Sheet
Low-Cost 16-bit DSP with
DDR Controller
• StarCore
• 192 Kbyte M2 memory for critical data and temporary data
• 8 Kbyte boot ROM.
• AHB-Lite crossbar switch that allows parallel data transfers
• Internal PLL generates up to 300 MHz clock for the SC1400 core
• Clock synthesis module provides predivision of PLL input clock;
• Enhanced 16-bit wide host interface (HDI16) provides a glueless
• DDR memory controller that supports byte enables for up to a
• Programmable memory interface with independent read buffers,
• System control unit performs software watchdog timer function;
• Event port collects and counts important signal events including
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
core, 256 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte
instruction cache (ICache), four-entry write buffer, programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
buffering.
between four master ports and six slave ports, where each port
connects to an AHB-Lite bus; fixed or round robin priority
programmable at each slave port; programmable bus parking at
each slave port; low power mode.
and up to 150 MHz for the crossbar switch, DMA channels, M2
memory, and other peripherals.
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
32-bit data bus; glueless interface to 150 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
programmable predictive read feature for each buffer, and a write
buffer.
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite master buses; and has address
out-of-range detection on each crossbar switch buses.
DMA and interrupt requests and trigger events such as interrupts,
breakpoints, DMA transfers, or wake-up events; units operate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
®
SC1400 DSP extended core with one SC1400 DSP
• Multi-channel DMA controller with 32 time-multiplexed
• Two independent TDM modules with independent receive and
• UART with full-duplex operation up to 5.0 Mbps.
• Up to 41 general-purpose input/output (GPIO) ports.
• I
• Two quad timer modules, each with sixteen configurable 16-bit
• fieldBIST™ unit detects and provides visibility into unlikely field
• Standard JTAG interface allows easy integration to system
• Optional booting external host via 8-bit or 16-bit access through
unidirectional channels, priority-based time-multiplexing
between channels using 32 internal priority levels, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
transmit, programmable sharing of frame sync and clock,
programmable word size (8 or 16-bit), hardware-base
A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to
128 channels, with glueless interface to E1/T1 frames and MVIP,
SCAS, and H.110 buses.
Mbyte.
timers.
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated speed, is free from
reliability defects, and reports diagnostics for partial or complete
device inoperability.
firmware and internal on-chip emulation (OCE10) module.
the HDI16, I
Flash/EEPROM devices; different clocking options during boot
with the PLL on or off using a variety of input frequency ranges.
2
C interface that allows booting from EEPROM devices up to 1
2
C, or SPI using in the boot ROM to access serial SPI
MSC7118
Document Number: MSC7118
MAP-BGA–400
17 mm × 17 mm
Rev. 7, 4/2008

Related parts for MSC7118

MSC7118 Summary of contents

Page 1

... DMA transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the OCE10. © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Document Number: MSC7118 MSC7118 MAP-BGA–400 17 mm × • Multi-channel DMA controller with 32 time-multiplexed ...

Page 2

... Package Information .56 6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 List of Figures Figure 1. MSC7118 Block Diagram Figure 2. MSC7118 Molded Array Process-Ball Grid Array (MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. MSC7118 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Timing Diagram for a Reset Configuration Write . . . . 25 Figure 5 ...

Page 3

... Cache (16 KB) Extended Core Interface M1 SRAM (256 KB) 128 Note: The arrows show the direction of the transfer. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor DMA AMDMA ASM2 128 64 to IPBus 64 DSP ASEMI Core 64 IPBus ASTH ...

Page 4

... Pin Assignments 1 Pin Assignments This section includes diagrams of the MSC7118 package ball grid array layouts and pinout allocation tables. 1.1 MAP-BGA Ball Layout Diagrams Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers. ...

Page 5

... W MDC RX_ER TXCLK TXD1 RXD3 Y RX_DV GND RXD1 TXD0 RXCLK Figure 3. MSC7118 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Bottom View GND HD0 HD1 HD4 ...

Page 6

... A17 A18 A19 A20 B10 B11 B12 B13 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GND GND DQM1 DQS2 CK CK GPIC7 GPOC7 GPIC4 GPOC4 ...

Page 7

... C12 C13 C14 C15 C16 C17 C18 C19 C20 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled NC GPID7 GPOD7 D24 D30 D25 ...

Page 8

... E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDM V DDIO V DDIO V DDIO V DDIO V DDIO ...

Page 9

... G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 H1 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDC GND GND GND V DDM V DDM GND ...

Page 10

... H20 J10 J11 J12 J13 J14 J15 J16 J17 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled D12 D11 V DDM V DDM GND GND GND GND ...

Page 11

... K16 K17 K18 K19 K20 L10 L11 L12 L13 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GPIC11 GPOC11 reserved reserved D0 GND D8 V DDC V ...

Page 12

... M14 M15 M16 M17 M18 GPIA14 M19 GPIA12 M20 GPIA13 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDIO V DDIO V DDIO V DDC GPIB11 GPOB11 reserved ...

Page 13

... P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GND GND GND GND GND V DDIO V DDC ...

Page 14

... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U1 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDM GND V DDM GND V DDM GND GND ...

Page 15

... V8 V9 V10 V11 SWTE V12 GPIA8 V13 GPIA4 V14 GPIA0 V15 GPIA28 V16 V17 GPIA22 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled D21 D23 V DDM V DDC V DDC ...

Page 16

... H8BIT reserved Y9 BM1 Y10 GPIA11 Y11 Y12 Y13 GPIA5 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled IRQ24 GPOA24 reserved TDI GND V DDM A12 A8 A7 ...

Page 17

... Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Signal Names ...

Page 18

... Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 3. Recommended Operating Conditions Rating Core supply voltage Memory supply voltage PLL supply voltage I/O supply voltage Reference voltage Operating temperature range MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Table 2. Absolute Maximum Ratings Symbol V DDC V DDM V ...

Page 19

... Thermal Characteristics Table 4 describes thermal characteristics of the MSC7118 for the MAP-BGA package. Table 4. Thermal Characteristics for MAP-BGA Package Characteristic 1, 2 Junction-to-ambient 1, 3 Junction-to-ambient, four-layer board 4 Junction-to-board 5 Junction-to-case 6 Junction-to-package-top Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance ...

Page 20

... V REF exceed ±2% of the DC value not applied directly to the MSC7118 device the level measured at the far end signal termination. It should be equal This rail should track variations in the DC level of V REF Output leakage for the memory interface is measured with all outputs disabled ≤ ...

Page 21

... The rise and fall time of external clocks should maximum Characteristic CLKIN frequency CLKIN slope CLKIN frequency jitter (peak-to-peak) CLKO frequency jitter (peak-to-peak) MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor ) ns load ) ns load ) clocks. You must ensure that maximum frequency values are not exceeded (see CLKO Table 6 ...

Page 22

... Electrical Characteristics 2.5.2 Configuring Clock Frequencies This section describes important requirements for configuring clock frequencies in the MSC7118 device when using the PLL block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL): • PLLDVF field. Specifies the PLL division factor (PLLDVF + 1) to divide the input clock frequency of the divider block is the input to the multiplier block. • ...

Page 23

... MHz DDR 266 (PC-2100) 83–133 MHz DDR 333 (PC-2600) 83–150 MHz MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Table 10. PLLMLTF Ranges Minimum PLLMLTF Value 266/Divided Input Clock . The minimum and maximum multiplication factors are dependent on the Loop Table 11 ...

Page 24

... Reset Timing The MSC7118 device has several inputs to the reset logic. All MSC7118 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 14 describes the reset sources. ...

Page 25

... Timings are not tested, but are guaranteed by design. 1 PORESET Input PORESET Internal HRESET Output (I/O) Figure 4. Timing Diagram for a Reset Configuration Write MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor C interface Characteristics Configuration Pins are sampled 2 Electrical Characteristics deassertion to define the boot and ...

Page 26

... An/RAS/CAS/WE/CKE output hold with respect to CK 206 CSn output setup with respect to CK 207 CSn output hold with respect 208 CK to DQSn MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Table 17. DDR DRAM Input AC Timing Symbol — ...

Page 27

... Figure 6 shows the DDR DRAM output timing diagram 204 206 An RAS CAS Write A0 WE CKE DQMn DQSn Dn Figure 6. DDR DRAM Output Timing Diagram MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Symbol 3 t DDKHDS, t DDKLDS 3 t DDKHDX, t DDKLDX t DDKHMP ...

Page 28

... Use of the rising edge or falling edge as a reference is programmable. Refer to the MSC711x Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge. TDMxRCK TDMxRD TDMxRFS TDMxRFS (output) MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Ω Figure 7 ...

Page 29

... TDMxTCK TDMxTD TDMxRCK TDMxTFS (output) TDMxTFS (input) MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor 300 301 307 306 310 305 303 Figure 9. TDM Transmit Signals Electrical Characteristics 302 309 308 311 29 ...

Page 30

... The read and write data strobe minimum deassertion width for non-”last data register” accesses in single and dual data strobe modes is based on timings 57 and 58. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Table 21. Host Interface (HDI16) Timing ...

Page 31

... Figure 10. Read Timing Diagram, Single Data Strobe HA[0–2] HCS[1–2] HRD HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 11. Read Timing Diagram, Double Data Strobe MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor HRW 44a ...

Page 32

... HTRQ (double host request) Figure 12. Write Timing Diagram, Single Data Strobe HA[0–2] HCS[1–2] HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 13. Write Timing Diagram, Double Data Strobe MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev ...

Page 33

... Figure 14. Host DMA Read Timing Diagram, HPCR[OAD HD[0–15] Figure 15. Host DMA Write Timing Diagram, HPCR[OAD MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor HREQ (Output) 64 44a RX[0–3] HACK Read 50 49 Data HD[0–15] Valid (Output) HREQ (Output TX[0– ...

Page 34

... SDA and SCL is 400 pF. Start Condition 1 SCL 451 SDA 458 Start Condition SCL SDA MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Table 22 Timing Min 0 (SCL clock period/2) – 0.3 (SCL clock period/2) – 0.3 (SCL clock period/2) – 0.1 2 × ...

Page 35

... Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details. 3. Refer to Table 1-11 on page 1-16 for details on EE pin functionality. Figure 20 shows the signal behavior of the EE0 In EE0 Out MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Table 23. UART Timing Expression F /2 ...

Page 36

... Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is acknowledged. Figure 21 shows the signal behavior of the GPI GPO MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Table 25. EVNT Signal Timing Type Asynchronous ...

Page 37

... Note: All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface. TCK (Input) Figure 22. Test Clock Input Timing Diagram MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Table 27. JTAG Timing × ...

Page 38

... TMS (Input) TDO (Output) TDO (Output) Figure 24. Test Access Port Timing Diagram TRST (Input) 712 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev 704 Input Data Valid 706 Output Data Valid 707 708 Input Data Valid 710 Output Data Valid 711 Figure 25 ...

Page 39

... I/O The power dissipation values for the MSC7118 are listed in Table 4. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes ...

Page 40

... Core Memory Reference I/O You should supply the MSC7118 core voltage via a variable switching supply or regulator to allow for compatibility with possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across V and GND and the I/O section is supplied with 3.3 V (± 10%) across V the DDR memory controller block. The memory voltage is supplied with 2.5 V across V and must be between 0.49 × ...

Page 41

... Make sure that the time interval between the ramp-up or ramp-down for V power-up and power-down. • Refer to Figure 26 for relative timing for power sequencing case 1. Ramp-up <10 ms <10 ms MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor and V DDIO <10 ms Time Figure 26. Voltage Sequencing Case 1 Hardware Design Considerations is less than 10 ms ...

Page 42

... Make sure that the time interval between the ramp-up or ramp-down for V power-up and power-down. • Refer to Figure 27 for relative timing for Case 2. Ramp-up <10 ms MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev (2.5 V) supplies simultaneously (second). DDM and V DDIO and V DDIO < ...

Page 43

... Make sure that the time interval between the ramp-up or ramp-down time for V power-up and power-down. • Refer to Figure 28 for relative timing for Case 3. Ramp-up <10 ms <10 ms MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor (1.25 V) supplies simultaneously (third). REF and V DDIO (1.25 V) supplies simultaneously (first). ...

Page 44

... Make sure that the time interval between the ramp-up or ramp-down time for V power-up and power-down. • Refer to Figure 29 for relative timing for Case 4. Ramp-up <10 ms MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev (2.5 V), and V (1.25 V) supplies simultaneously (second). DDM REF ...

Page 45

... If a design uses case 5, it must accommodate DDM the potential current spikes. Verify risks related to current spikes using actual information for the specific application. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor and V ...

Page 46

... The second decoupling level should consist of two bulk/tantalum decoupling capacitors, one 10 μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7118 voltage pins. Additionally, the maximum drop between the power supply and the DSP device should ...

Page 47

... V, and the core frequency is 300 MHz. This yields: = 750 pF × (1 CORE This equation allows for adjustments to voltage and frequency if necessary. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Symbol Nominal Voltage V 1 ...

Page 48

... Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage, termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7118 device, the 2.5 V power source provides the power for the termination, which is a static value per signal driven high. ...

Page 49

... Either a smaller value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7118 output current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design). ...

Page 50

... After the boot program is loaded, it can enable the PLL and start the device operating at a higher speed. The MSC7118 can boot from an external host through the HDI16 or download a user program through the I boot operating mode is set by configuring the See the MSC711x Reference Manual for details of boot program operation ...

Page 51

... Then the MSC7118 device initiates accesses to the SPI module, downloading data to the MSC7118 device. When the SPI routines run in the boot ROM, the MSC7118 is always configured as the SPI master. Booting through the SPI is supported for serial EEPROM devices and serial Flash devices. When a READ_ID instruction is issued to the serial memory device and the device returns a value of 0x00 or 0xFF, the routines for accessing a serial EEPROM are used maximum frequency of 4 Mbps ...

Page 52

... Hardware Design Considerations 3.5 DDR Memory System Guidelines MSC7118 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown in Figure 32. Technique B is the most popular termination technique. ...

Page 53

... TT termination rail. • See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel ( http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf ). MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor ...

Page 54

... If stack-up allows, keep DDR data groups away from the address and control nets. — Route address and control on separate critical layers. — If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages. MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev DQS ...

Page 55

... Connectivity Guidelines This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7118 device. Following are guidelines for signal groups and configuration settings: • Clock and reset signals. — is used to configure the MSC7118 device and is sampled on the deassertion of ...

Page 56

... MSC711x Reference Manual (MSC711xRM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. • Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC7118 device. • SC140/SC1400 DSP Core Reference Manual. Covers the SC140 and SC1400 core architecture, control registers, clock registers, program control, and instruction set ...

Page 57

... Section 3.2 has been clarified by adding subsection headings. • Change the PLL filter resistor from 20 Ω Ω in Section 3.2.5. 7 Apr 2008 MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Table 32. Document Revision History Description and V ...

Page 58

... Revision History MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Freescale Semiconductor ...

Page 59

... MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7 Freescale Semiconductor Revision History 59 ...

Page 60

... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MSC7118 Rev. 7 4/2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...

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