MSC7118 Freescale Semiconductor / Motorola, MSC7118 Datasheet - Page 24

• Manufacturer Part Number: MSC7118
• Description: Low-Cost 16-bit DSP with DDR Controller
• Manufacturer: Freescale Semiconductor / Motorola

Electrical Characteristics
2.5.3
The MSC7118 device has several inputs to the reset logic. All MSC7118 reset sources are fed into the reset controller, which
takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause
a reset. Table 14 describes the reset sources.
Table 15 summarizes the reset actions that occur as a result of the different reset sources.
2.5.3.1
Asserting
external power to the MSC7118 reaches at least 2/3
24
Power-on reset
(PORESET)
External Hard
reset (HRESET)
Software
watchdog reset
Bus monitor
reset
JTAG EXTEST,
CLAMP, or
HIGHZ command
Configuration pins sampled (refer to Section 2.5.3.1 for
details).
PLL and clock synthesis states Reset
HRESET Driven
Software watchdog and bus time-out monitor registers
Clock synthesis modules (STOPCTRL, HLTREQ, and
HLTACK) reset
Extended core reset
Peripheral modules reset
Name
PORESET
Reset Timing
Reset Action/Reset Source
Power-On Reset (PORESET) Pin
Input/ Output
initiates the power-on reset flow.
Direction
Internal
Internal
Internal
Input
MSC7118 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 7
Table 15. Reset Actions for Each Reset Source
Initiates the power-on reset flow that resets the MSC7118 and configures various attributes of the
MSC7118. On PORESET, the entire MSC7118 device is reset. SPLL and DLL states are reset,
HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The
system is configured only when PORESET is asserted.
Initiates the hard reset flow that configures various attributes of the MSC7118. While HRESET is
asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400
extended core is reset.
When the MSC7118 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
When the MSC7118 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic
asserts an internal reset signal that generates an internal soft reset sequence.
Table 14. Reset Sources
V
DD
PORESET
.
Power-On Reset
External only
(PORESET)
must be asserted externally for at least 16
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Description
Internal (Software
Watchdog or Bus
Hard Reset
External or
(HRESET)
Monitor)
Yes
Yes
Yes
Yes
Yes
No
No
Freescale Semiconductor
EXTEST, CLAMP,
JTAG Command:
CLKIN
Soft Reset
(SRESET)
or HIGHZ
Yes
Yes
Yes
Yes
No
No
No
cycles after