MSC7119 Freescale Semiconductor / Motorola, MSC7119 Datasheet
MSC7119
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MSC7119 Summary of contents
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... DMA transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the OCE10. © Freescale Semiconductor, Inc., 2004, 2007. All rights reserved. Document Number: MSC7119 MSC7119 MAP-BGA–400 17 mm × • Multi-channel DMA controller with 32 time-multiplexed ...
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... Package Information .53 6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 List of Figures Figure 1. MSC7119 Block Diagram Figure 2. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Timing Diagram for a Reset Configuration Write . . . . 25 Figure 5 ...
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... Instruction Cache (16 KB) Extended Core Interface M1 SRAM (256 KB) 128 Note: The arrows show the direction of the transfer. MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor DMA AMDMA ASM2 128 64 to IPBus 64 DSP ASEMI Core 64 IPBus ASTH AMIC ...
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... Pin Assignments 1 Pin Assignments This section includes diagrams of the MSC7119 package ball grid array layouts and pinout allocation tables. 1.1 FC-PBGA Ball Layout Diagrams Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers. ...
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... RXD0 RXD2 W MDC RX_ER TXCLK TXD1 RXD3 Y RX_DV GND RXD1 TXD0 RXCLK Figure 3. MSC7119 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Bottom View GND HD0 HD1 HD4 ...
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... BM3 A17 A18 A19 A20 B10 B11 B12 B13 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GND GND DQM1 DQS2 CK CK GPIC7 GPOC7 GPIC4 GPOC4 GPIC2 ...
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... C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled NC GPID7 GPOD7 D24 D30 D25 CS1 ...
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... E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDM V DDIO V DDIO V DDIO V DDIO V DDIO V DDIO ...
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... G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 H1 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDC GND GND GND V DDM V DDM GND GND ...
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... H19 H20 J10 J11 J12 J13 J14 J15 J16 J17 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled D12 D11 V DDM V DDM GND GND GND GND GND ...
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... K15 K16 K17 K18 K19 K20 L10 L11 L12 L13 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GPIC11 GPOC11 reserved reserved D0 GND D8 V DDC V DDM ...
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... M13 M14 M15 M16 M17 M18 GPIA14 M19 GPIA12 M20 GPIA13 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDIO V DDIO V DDIO V DDC GPIB11 GPOB11 reserved reserved ...
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... P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GND GND GND GND GND V DDIO V DDC V DDC ...
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... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U1 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDM GND V DDM GND V DDM GND GND V DDIO ...
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... V10 V11 SWTE V12 GPIA8 V13 GPIA4 V14 GPIA0 V15 GPIA28 V16 V17 GPIA22 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled D21 D23 V DDM V DDC V DDC V DDC ...
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... W20 H8BIT reserved Y9 BM1 Y10 GPIA11 Y11 Y12 Y13 GPIA5 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled IRQ24 GPOA24 reserved TDI GND V DDM A12 ...
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... The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Signal Names ...
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... Electrical Characteristics Table 2 describes the maximum electrical ratings for the MSC7119. Rating Core supply voltage Memory supply voltage PLL supply voltage I/O supply voltage Input voltage Reference voltage Maximum operating temperature Minimum operating temperature Storage temperature range Notes: 1. Functional operating conditions are given in Table 3. ...
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... Thermal Characteristics Table 4 describes thermal characteristics of the MSC7119 for the MAP-BGA package. Table 4. Thermal Characteristics for MAP-BGA Package Characteristic 1, 2 Junction-to-ambient 1, 3 Junction-to-ambient, four-layer board 4 Junction-to-board 5 Junction-to-case 6 Junction-to-package-top Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance ...
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... V REF exceed ±2% of the DC value not applied directly to the MSC7119 device the level measured at the far end signal termination. It should be equal This rail should track variations in the DC level of V REF Output leakage for the memory interface is measured with all outputs disabled ≤ ...
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... The rise and fall time of external clocks should maximum Characteristic CLKIN frequency CLKIN slope CLKIN frequency jitter (peak-to-peak) CLKO frequency jitter (peak-to-peak) MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor ) ns load ) ns load ) clocks. You must ensure that maximum frequency values are not exceeded (see CLKO Table 6 ...
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... Electrical Characteristics 2.5.2 Configuring Clock Frequencies This section describes important requirements for configuring clock frequencies in the MSC7119 device when using the PLL block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL): • PLLDVF field. Specifies the PLL division factor (PLLDVF + 1) to divide the input clock frequency of the divider block is the input to the multiplier block. • ...
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... DDR 200 (PC-1600) 83–100 MHz DDR 266 (PC-2100) 83–133 MHz DDR 333 (PC-2600) 83–150 MHz MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Table 10. PLLMLTF Ranges Minimum PLLMLTF Value 266/Divided Input Clock . The minimum and maximum multiplication factors are dependent on the Loop Table 11 ...
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... Reset Timing The MSC7119 device has several inputs to the reset logic. All MSC7119 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 14 describes the reset sources. ...
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... Reset Configuration The MSC7119 has two mechanisms for writing the reset configuration: • From a host through the host interface (HDI16) 2 • From memory through the I Five signal levels (see Chapter 1 for signal description details) are sampled on operating conditions: • BM[0–1] • ...
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... An/RAS/CAS/WE/CKE output hold with respect to CK 206 CSn output setup with respect to CK 207 CSn output hold with respect 208 CK to DQSn MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Table 17. DDR DRAM Input AC Timing Symbol — ...
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... Figure 6 shows the DDR DRAM output timing diagram 204 206 An RAS CAS Write A0 WE CKE DQMn DQSn Dn Figure 6. DDR DRAM Output Timing Diagram MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Symbol 3 t DDKHDS, t DDKLDS 3 t DDKHDX, t DDKLDX t DDKHMP ...
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... Use of the rising edge or falling edge as a reference is programmable. Refer to the MSC711x Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge. TDMxRCK TDMxRD TDMxRFS TDMxRFS (output) MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Ω Figure 7 ...
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... RXDn, RX_DV, CRS_DV, RX_ER to receive clock rising edge setup time 804 Receive clock rising edge to RXDn, RX_DV, CRS_DV, RX_ER hold time Receive clock RXDn RX_DV CRS_DV RX_ER MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor 300 301 307 306 310 305 303 Figure 9 ...
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... MII: CRS and COL minimum pulse width (1.5 × TXCLK period) 807 • RMII: CRS_DV minimum pulse width (1.5 x REFCLK period) CRS COL CRS_DV Figure 12. Asynchronous Input Signal Timing MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Table 22. Transmit Signal Timing Characteristics 800 801 806 805 Figure 11 ...
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... MDIO input to MDC rising edge setup time 814 MDC rising edge to MDIO input hold time MDC (output) MDIO (output) MDIO (input) Figure 13. Serial Management Channel Timing MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Characteristics 808 809 811 813 ...
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... Compute the value using the expression. 12. The read and write data strobe minimum deassertion width for non-”last data register” accesses in single and dual data strobe modes is based on timings 57 and 58. MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Table 25. Host Interface (HDI16) Timing ...
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... Figure 14. Read Timing Diagram, Single Data Strobe HA[0–2] HCS[1–2] HRD HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 15. Read Timing Diagram, Double Data Strobe MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor HRW 44a ...
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... HTRQ (double host request) Figure 16. Write Timing Diagram, Single Data Strobe HA[0–2] HCS[1–2] HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 17. Write Timing Diagram, Double Data Strobe MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev ...
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... Figure 18. Host DMA Read Timing Diagram, HPCR[OAD HD[0–15] Figure 19. Host DMA Write Timing Diagram, HPCR[OAD MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor HREQ (Output) 64 44a RX[0–3] HACK Read 50 49 Data HD[0–15] Valid (Output) HREQ (Output TX[0–3] Write ...
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... SDA set-up time is referenced to the rising edge of SCL. SDA hold time is referenced to the falling edge of SCL. Load capacitance on SDA and SCL is 400 pF. Start Condition 1 SCL 451 SDA 458 Start Condition SCL SDA MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Table 26 Timing Min 0 (SCL clock period/2) – 0.3 (SCL clock period/2) – 0.3 (SCL clock period/2) – 0.1 2 × 1/F ...
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... Configure the direction of the EE pin in the EE_CTRL register (see the SC140/SC1400 Core Reference Manual for details. 3. Refer to Table 1-11 on page 1-16 for details on EE pin functionality. Figure 24 shows the signal behavior of the EE0 In EE0 Out MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Table 27. UART Timing Expression F /2 ...
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... Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is acknowledged. Figure 25 shows the signal behavior of the GPI GPO MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Table 29. EVNT Signal Timing Type Asynchronous Synchronous to core clock ...
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... TRST assert time Note: All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface. TCK (Input) Figure 26. Test Clock Input Timing Diagram MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Table 31. JTAG Timing × 1.6 V ...
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... TMS (Input) TDO (Output) TDO (Output) Figure 28. Test Access Port Timing Diagram TRST (Input) 712 MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev 704 Input Data Valid 706 Output Data Valid 707 708 Input Data Valid 710 Output Data Valid 711 Figure 29 ...
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... I/O The power dissipation values for the MSC7119 are listed in Table 4. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes ...
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... Voltage Core Memory Reference I/O You should supply the MSC7119 core voltage via a variable switching supply or regulator to allow for compatibility with possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across V and GND and the I/O section is supplied with 3.3 V (± 10%) across V DDC reference voltages supply the DDR memory controller block ...
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... The second decoupling level should consist of two bulk/tantalum decoupling capacitors, one 10 μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7119 voltage pins. Additionally, the maximum drop between the power supply and the DSP device should ...
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... V, and the core frequency is 300 MHz. This yields: = 750 pF × (1 CORE This equation allows for adjustments to voltage and frequency if necessary. MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev and timer modules. Table 33. Recommended Power Supply Ratings ...
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... Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage, termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7119 device, the 2.5 V power source provides the power for the termination, which is a static value per signal driven high. ...
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... Either a smaller value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7119 output current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design). ...
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... After the boot program is loaded, it can enable the PLL and start the device operating at a higher speed. The MSC7119 can boot from an external host through the HDI16 or download a user program through the I boot operating mode is set by configuring the See the MSC711x Reference Manual for details of boot program operation ...
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... SPI Boot When the MSC7119 device is configured to boot from the SPI port, the boot program configures the GPIO pins for SPI operation. Then the MSC7118 device initiates accesses to the SPI module, downloading data to the MSC7118 device. When the SPI routines run in the boot ROM, the MSC7118 is always configured as the SPI master. Booting through the SPI is supported for serial EEPROM devices and serial Flash devices ...
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... DDR Memory System Guidelines MSC7119 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown in Figure 32. Technique B is the most popular termination technique. ...
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... TT termination rail. • See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel (http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf). MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev ...
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... If stack-up allows, keep DDR data groups away from the address and control nets. — Route address and control on separate critical layers. — If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages. MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor DQS ...
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... Ordering Information 3.6 Connectivity Guidelines This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7119 device. Following are guidelines for signal groups and configuration settings: • Clock and reset signals. — is used to configure the MSC7119 device and is sampled on the deassertion of ...
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... MSC711x Reference Manual (MSC711xRM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. • Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC7119 device. • SC140/SC1400 DSP Core Reference Manual. Covers the SC140 and SC1400 core architecture, control registers, clock registers, program control, and instruction set ...
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... Updated to new data sheet format. Reorganized and renumbered sections, figures, and tables. • Added a note to clarify the definition of TCK timing 700 in new Table 31. • Removed references to V 3.2. MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev Table 36. Document Revision History Description ...
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... MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6 Freescale Semiconductor Revision History 55 ...
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... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MSC7119 Rev. 6 7/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...